Heechun Park - RankMe

40 papers A* 3A 8B 1C 1Journal 12Unranked 15

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	SMT-Based Optimal Transistor Folding and Placement for Standard Cell Layout Generation. ASP-DAC Junghyun Yoon, Heechun Park
2026	—	`conf`	Standard Cell Layout Generation: Methodological Evolution and Architectural Impacts. ASP-DAC Junghyun Yoon, Ikkyum Kim, Gyumin Kim, Sojung Park, Heechun Park
2025	A	`conf`	A Unified Design Flow for Homogeneous and Heterogeneous 3D Integration with Fine-Pitch Hybrid Bonding. ICCAD Gyumin Kim, Heechun Park
2025	—	`conf`	Clustering-Driven Bonding Terminal Legalization with Reinforcement Learning for F2F 3D ICs. ASP-DAC Gyumin Kim, Heechun Park
2025	A*	`conf`	Mitigating Routability Problems in Complementary-FET-based VLSI Designs. DAC Junghyun Yoon, Heechun Park
2025	—	`conf`	PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation. ASP-DAC Eunsol Jeong, Taewhan Kim, Heechun Park
2025	—	`conf`	Priority-Aware Routing Optimization with Full-Path Delay Prediction Using Machine Learning. MLCAD Hyunmin Jo, Heechun Park
2025	A	`conf`	Timing-Driven Detailed Placement with Unsupervised Graph Learning. DATE Dhoui Lim, Heechun Park
2025	A	`conf`	Timing-Driven Macro Placement with Connectivity-Aware Clustering. ISLPED Gangmin Jeon, Heechun Park
2024	—	`conf`	3T1R Memristor Crossbar Architecture for Diverse Logic Implementation. ISOCC Ikkyum Kim, Heechun Park
2024	J	`jnl`	Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Suwan Kim, Heechun Park
2024	J	`jnl`	DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaehoon Ahn, Kyungjoon Chang, Kyumyung Choi, Taewhan Kim, Heechun Park
2024	—	`conf`	Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations. ISQED Junghyun Yoon, Heechun Park
2024	—	`conf`	Double-Row Flip-flop Design Under Advanced Technology and Its IC-Level Effects. ISOCC Yoonjae Lee, Heechun Park
2024	—	`conf`	Graph Neural Network-Based Detailed Placement Optimization Framework. ISQED Dho Ui Lim, Heechun Park
2024	C	`conf`	Memristive Logic-in-Memory Implementation with Area Efficiency and Parallelism. ICCD Ikkyum Kim, Heechun Park
2024	—	`conf`	Timing-Aware Tier Partitioning for 3D ICs with Critical Path Consideration. ICEIC Sojung Park, Heechun Park
2023	A	`conf`	DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. DATE Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim
2023	J	`jnl`	Eliminating Minimum Implant Area Violations With Design Quality Preservation. IEEE Trans. Very Large Scale Integr. Syst. Eunsol Jeong, Taewhan Kim, Heechun Park
2022	A	`conf`	A Systematic Removal of Minimum Implant Area Violations under Timing Constraint. DATE Eunsol Jeong, Heechun Park, Taewhan Kim
2022	J	`jnl`	Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs. ACM J. Emerg. Technol. Comput. Syst. Arjun Chaudhuri, Sanmitra Banerjee, Jinwoo Kim, Heechun Park, Bon Woong Ku, Sukeshwar Kannan, Krishnendu Chakrabarty, Sung Kyu Lim
2022	J	`jnl`	Speeding-up neuromorphic computation for neural networks: Structure optimization approach. Integr. Heechun Park, Taewhan Kim
2022	A	`conf`	Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. ISLPED Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park
2021	J	`jnl`	Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach. IEEE Trans. Very Large Scale Integr. Syst. Taehwan Kim, Heechun Park, Taewhan Kim
2021	—	`conf`	Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology. ISOCC Heechun Park, Kyungjoon Chang, Jooyeon Jeong, Jaehoon Ahn, Ki-Seok Chung, Taewhan Kim
2021	J	`jnl`	Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems. IEEE Trans. Very Large Scale Integr. Syst. Gauthaman Murali, Heechun Park, Eric Qin, Hakki Mert Torun, Majid Ahadi Dolatsara, Madhavan Swaminathan, Tushar Krishna, Sung Kyu Lim
2021	—	`conf`	Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement. MWSCAS Eunsol Jeong, Heechun Park, Jooyeon Jeong, Taewhan Kim
2021	J	`jnl`	Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements. ACM Trans. Design Autom. Electr. Syst. Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim
2021	—	`conf`	Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis. ISOCC Seyoung Kim, Heechun Park, Jaeha Kim
2020	J	`jnl`	Advances in Design and Test of Monolithic 3-D ICs. IEEE Des. Test Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Jinwoo Kim, Gauthaman Murali, Edward Lee, Daehyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay, Krishnendu Chakrabarty
2020	J	`jnl`	Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse. IEEE Trans. Very Large Scale Integr. Syst. Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim
2020	—	`conf`	Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs. ISPD Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim
2019	A*	`conf`	Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse. DAC Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim
2019	B	`conf`	Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs. ETS Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Bon Woong Ku, Krishnendu Chakrabarty, Sung Kyu Lim
2019	J	`jnl`	Hybrid asynchronous circuit generation amenable to conventional EDA flow. Integr. Heechun Park, Taewhan Kim
2019	A*	`conf`	RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs. DAC Heechun Park, Kyungwook Chang, Bon Woong Ku, Jinwoo Kim, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Saibal Mukhopadhyay, Krishnendu Chakrabarty, Sung Kyu Lim
2018	A	`conf`	Structure optimizations of neuromorphic computing architectures for deep neural network. DATE Heechun Park, Taewhan Kim
2016	—	`conf`	Synthesizing Asynchronous Circuits toward Practical Use. ISVLSI Heechun Park, Taewhan Kim
2015	J	`jnl`	Synthesis of TSV Fault-Tolerant 3-D Clock Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Heechun Park, Taewhan Kim
2013	A	`conf`	Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees. ICCAD Heechun Park, Taewhan Kim