He Zhang

35 papers A* 2A 3C 1Journal 16Unranked 13
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 40 nm Buffer-Free 7T-SRAM Analog Charge-Domain CIM Macro With Merging Timing Based On Time-Row Division Strategy.
IEEE Trans. Very Large Scale Integr. Syst.
Linjun Jiang, Jianxin Wu, Sifan Sun, Changyu Li, Wang Kang, He Zhang
2026 J jnl
High-performance true random number generator based on SOT-MTJ spin relaxation.
Sci. China Inf. Sci.
Jialiang Yin, Xiuye Zhang, Boyan Zhang, Bolin Zhang, Wenlong Cai, Ao Du, Binchao Tang, Haowei Zhang, Shijian Bao, Chunyi Li, Daoqian Zhu, Kewen Shi, Hongxi Liu, Lang Zeng, He Zhang, Kaihua Cao, Weisheng Zhao
2026 J jnl
Self-Calibrating Analog Circuitry for Softmax-Scaled Function With Analog Computing-In-Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Linjun Jiang, Yitong Zhou, He Zhang, Wang Kang
2025 J jnl
A 0.88 e‾
IEEE Trans. Circuits Syst. I Regul. Pap.
Jianxin Wu, Wenjie Li, Wang Kang, Jing Kou, Liang Zhang, Liangchen Li, He Zhang, Weisheng Zhao
2025 — conf
A 24.65 TOPS/W@INT8 Hybrid Analog-Digital Multi-core SRAM CIM Macro with Optimal Weight Dividing and Resource Allocation Strategies.
ASP-DAC
Yitong Zhou, Wente Yi, Sifan Sun, Wenjia Wang, Jinyu Bai, He Zhang, Wang Kang
2025 A conf
An Adaptive Sparse Matrix Compression CIM Accelerator based on 256Kb SOT-MRAM for Downlink Massive MIMO Communications.
ICCAD
Liangchen Li, Jianxin Wu, Changyu Li, Liang Zhang, Anyang Yu, Junda Zhao, Zhaohao Wang, Chengyuan Sun, Kaihua Cao, Hongxi Liu, Wang Kang, He Zhang, Weisheng Zhao
2025 J jnl
HiT-CIM: A High-Throughput Compute-in-Memory SRAM Architecture With Simultaneous Weight Loading/Computing and Balance Capabilities.
IEEE Trans. Emerg. Top. Comput.
Junzhan Liu, Sifan Sun, Liang Zhang, Lichuan Luo, Liang Ran, He Zhang, Wang Kang, Weisheng Zhao
2025 J jnl
Model quantization for computing-in-memory: a survey.
Sci. China Inf. Sci.
Sifan Sun, Jinyu Bai, Hanting Chen, Kaiwen Deng, Zhiwei Xie, Jingjing Li, Bin Cao, He Zhang, Wang Kang, Weisheng Zhao
2025 — conf
Thermal-Compensated MRAM Sensing: Dynamic TMR Stabilization Across Wide Temperature Range.
MOCAST
Tuo Zhang, Xinpeng Jiang, Chao Wang, Bi Wang, Hongxi Liu, Kaihua Cao, Xuan Li, Hui Jin, Geifei Wang, Zhaohao Wang, He Zhang, Weisheng Zhao
2024 J jnl
CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets.
IEEE Trans. Circuits Syst. I Regul. Pap.
Lichuan Luo, Erya Deng, Dijun Liu, Zhen Wang, Weiliang Huang, He Zhang, Xiao Liu, Jinyu Bai, Junzhan Liu, Youguang Zhang, Wang Kang
2024 J jnl
Erratum to "A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks".
IEEE J. Emerg. Sel. Topics Circuits Syst.
Lichuan Luo, Wang Kang, Junzhan Liu, He Zhang, Youguang Zhang, Dijun Liu, Peng Ouyang
2024 — conf
MixMixQ: Quantization with Mixed Bit-Sparsity and Mixed Bit-Width for CIM Accelerators.
ACM Great Lakes Symposium on VLSI
Jinyu Bai, He Zhang, Wang Kang
2024 J jnl
PipeCIM: A High-Throughput Computing-In-Memory Microprocessor With Nested Pipeline and RISC-V Extended Instructions.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tingran Chen, Wenjia Wang, Jiaqi Chen, Haotian Fu, Wente Yi, Bojun Cheng, He Zhang, Biao Pan
2024 A* conf
Series-Parallel Hybrid SOT-MRAM Computing-in-Memory Macro with Multi-Method Modulation for High Area and Energy Efficiency.
DAC
Weiliang Huang, Jinyu Bai, Wang Kang, Zhaohao Wang, Kaihua Cao, Hongxi Liu, He Zhang, Weisheng Zhao
2024 J jnl
Toward Energy-efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems.
ACM Trans. Embed. Comput. Syst.
Yueting Li, Xueyan Wang, He Zhang, Biao Pan, Keni Qiu, Wang Kang, Jun Wang, Weisheng Zhao
2023 J jnl
A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Lichuan Luo, Wang Kang, Junzhan Liu, He Zhang, Youguang Zhang, Dijun Liu, Peng Ouyang
2023 — conf
A Robust Time-based Error-Proofing Readout Scheme for MRAM.
NANOARCH
Qianlei Ou, Shixing Li, Chao Wang, He Zhang, Zhaohao Wang
2023 — conf
An In-Memory-Computing STT-MRAM Macro with Analog ReLU and Pooling Layers for Ultra-High Efficient Neural Network.
NVMSA
Linjun Jiang, Sifan Sun, Jinming Ge, He Zhang, Wang Kang
2023 — conf
Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing Architecture.
ASP-DAC
Yueting Li, He Zhang, Xueyan Wang, Hao Cai, Yundong Zhang, Shuqin Lv, Renguang Liu, Weisheng Zhao
2022 J jnl
A Mini Tutorial of Processing in Memory: From Principles, Devices to Prototypes.
IEEE Trans. Circuits Syst. II Express Briefs
Biao Pan, Guangyao Wang, He Zhang, Wang Kang, Weisheng Zhao
2022 J jnl
A Spintronic In-Memory Computing Network for Efficient Hamming Codec Implementation.
IEEE Trans. Circuits Syst. II Express Briefs
Linjun Jiang, Erya Deng, He Zhang, Zhaohao Wang, Wang Kang, Weisheng Zhao
2022 A* conf
CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory.
DAC
He Zhang, Linjun Jiang, Jianxin Wu, Tingran Chen, Junzhan Liu, Wang Kang, Weisheng Zhao
2022 J jnl
HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM to Reduce Weight Loading Energy of Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
He Zhang, Junzhan Liu, Jinyu Bai, Sai Li, Lichuan Luo, Shaoqian Wei, Jianxin Wu, Wang Kang
2022 J jnl
SpinCIM: spin orbit torque memory for ternary neural networks based on the computing-in-memory architecture.
CCF Trans. High Perform. Comput.
Lichuan Luo, Dijun Liu, He Zhang, Youguang Zhang, Jinyu Bai, Wang Kang
2021 — conf
A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output.
ICTA
He Zhang, Junzhan Liu, Wang Kang, Yunqian Fan, Shufeng Fu, Jinyu Bai, Biao Pan, Yongpan Liu, Weisheng Zhao
2021 A conf
SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture.
DATE
Lichuan Luo, He Zhang, Jinyu Bai, Youguang Zhang, Wang Kang, Weisheng Zhao
2020 — conf
Deep Neural Network accelerator with Spintronic Memory.
ACM Great Lakes Symposium on VLSI
He Zhang, Wang Kang, Youguang Zhang, Weisheng Zhao
2020 A conf
High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques.
DATE
Haotian Wang, Wang Kang, Liuyang Zhang, He Zhang, Brajesh Kumar Kaushik, Weisheng Zhao
2019 — conf
Spintronic Memories: From Memory to Computing-in-Memory.
NANOARCH
Wang Kang, He Zhang, Weisheng Zhao
2018 J jnl
A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM.
IEEE Access
He Zhang, Wang Kang, Youguang Zhang, Meng-Fan Chang, Weisheng Zhao
2018 — conf
A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation.
NANOARCH
Chaoxin Ding, Wang Kang, He Zhang, Youguang Zhang, Weisheng Zhao
2018 — conf
High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory.
APCCAS
He Zhang, Wang Kang, Zhaohao Wang, Erya Deng, Youguang Zhang, Weisheng Zhao
2017 — conf
Advanced Low Power Spintronic Memories beyond STT-MRAM.
ACM Great Lakes Symposium on VLSI
Wang Kang, Zhaohao Wang, He Zhang, Sai Li, Youguang Zhang, Weisheng Zhao
2017 C conf
Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device.
ICCD
Wang Kang, He Zhang, Peng Ouyang, Youguang Zhang, Weisheng Zhao
2016 — conf
Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM.
NANOARCH
He Zhang, Wang Kang, Tingting Pang, Weifeng Lv, Youguang Zhang, Weisheng Zhao