He Gong Wei

16 papers C 1Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2020 J jnl
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration.
IEEE J. Solid State Circuits
Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
2020 J jnl
A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications.
IEEE Access
Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
2019 — conf
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration.
CICC
Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
2019 — conf
A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing.
VLSI Circuits
Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
2012 — conf
A 0.024 mm
ESSCIRC
Guohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins
2012 J jnl
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC.
IEEE J. Solid State Circuits
He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2011 — conf
A 0.024mm
ISSCC
He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2010 J jnl
A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2010 — conf
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H.
ESSCIRC
Sai-Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2010 — conf
An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications.
ICECS
Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang
2010 J jnl
Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC.
IEEE Trans. Circuits Syst. II Express Briefs
U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2010 J jnl
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs.
VLSI Design
Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008 C conf
A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier.
ISCAS
He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008 — conf
A power-efficient capacitor structure for high-speed charge recycling SAR ADCs.
ICECS
Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008 — conf
A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.
APCCAS
He Gong Wei, U. Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
2008 — conf
A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs.
APCCAS
U. Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins