Hayate Okuhara

40 papers A 1B 3C 1Journal 16Unranked 19

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. IEEE J. Solid State Circuits Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini
2024	—	`conf`	SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. COOL CHIPS Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida
2023	—	`conf`	55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes. ISSCC Karim Ali Ahmed, Hayate Okuhara, Massimo Alioto
2023	—	`conf`	A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. ISSCC Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, Mathieu Louvat, Emmanuel Botte, Luca Benini
2023	J	`jnl`	A Scalable Body Bias Optimization Method Toward Low-Power CGRAs. IEEE Micro Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano
2023	J	`jnl`	Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. CoRR Francesco Conti, Gianna Paulin, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini
2022	—	`conf`	Body Bias Control on a CGRA based on Convex Optimization. COOL CHIPS Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano
2021	J	`jnl`	A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL. IEEE Trans. Circuits Syst. II Express Briefs Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini
2021	J	`jnl`	A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi
2021	J	`jnl`	A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS. CoRR Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi
2020	J	`jnl`	A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL. CoRR Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini
2020	C	`conf`	An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. ISCAS Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Palestri, Luca Benini
2020	J	`jnl`	An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. CoRR Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Palestri, Luca Benini
2020	J	`jnl`	Flexible Software-Defined Packet Processing Using Low-Area Hardware. IEEE Access Hesam Zolfaghari, Davide Rossi, Walter Cerroni, Hayate Okuhara, Carla Raffaelli, Jari Nurmi
2019	—	`conf`	A Preliminary Evaluation of Building Block Computing Systems. MCSoC Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Mitaro Namiki
2019	—	`conf`	A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration. MCSoC Hayate Okuhara, Ryosuke Kazami, Hideharu Amano
2019	—	`conf`	Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process. CANDAR Workshops Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano
2018	—	`conf`	Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. MCSoC Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2018	J	`jnl`	Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach. IEICE Trans. Inf. Syst. Carlos Cesar Cortes Torres, Hayate Okuhara, Nobuyuki Yamasaki, Hideharu Amano
2018	J	`jnl`	Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization. IEEE Trans. Very Large Scale Integr. Syst. Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano
2018	J	`jnl`	Body Bias Control for Renewable Energy Source with a High Inner Resistance. IEEE Trans. Multi Scale Comput. Syst. Keita Azegami, Hayate Okuhara, Hideharu Amano
2018	—	`conf`	Design automation methodology of a critical path monitor for adaptive voltage controls. COOL CHIPS Ryosuke Kazami, Hayate Okuhara, Hideharu Amano
2018	J	`jnl`	Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Hayate Okuhara, Akram Ben Ahmed, Hideharu Amano
2018	J	`jnl`	Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures. IEICE Trans. Inf. Syst. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano
2018	—	`conf`	Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping. HEART Takuya Kojima, Naoki Ando, Yusuke Matshushita, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano
2017	J	`jnl`	Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator. IEICE Trans. Inf. Syst. Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
2017	—	`conf`	Body bias control for renewable energy source with a high inner resistance. COOL Chips Keita Azegami, Hayate Okuhara, Hideharu Amano
2017	B	`conf`	Body bias optimization for variable pipelined CGRA. FPL Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano
2017	—	`conf`	Glitch-aware variable pipeline optimization for CGRAs. ReConFig Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano
2017	—	`conf`	Leveraging asymmetric body bias control for low power LSI design. COOL Chips Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano
2017	—	`conf`	Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA. MCSoC Nguyen Anh Vu Doan, Yusuke Matsushita, Naoki Ando, Hayate Okuhara, Hideharu Amano
2017	J	`jnl`	Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET. IEEE Trans. Very Large Scale Integr. Syst. Hayate Okuhara, Yu Fujita, Kimiyoshi Usami, Hideharu Amano
2016	B	`conf`	Body bias grain size exploration for a coarse grained reconfigurable accelerator. FPL Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
2016	—	`conf`	MuCCRA4-BB: A fine-grained body biasing capable DRP. COOL Chips Johannes Maximilian Kühn, Akram Ben Ahmed, Hayate Okuhara, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel
2016	—	`conf`	Variable pipeline structure for Coarse Grained Reconfigurable Array CMA. FPT Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano
2015	B	`conf`	7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2. FPL Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano
2015	—	`conf`	A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. ReConFig Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano
2015	—	`conf`	A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control. COOL Chips Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano
2015	A	`conf`	An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET. ISLPED Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano
2015	—	`conf`	Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB. CANDAR Yu Fujita, Hayate Okuhara, Koichiro Masuyama, Hideharu Amano