Hasan Erdem Yantir

22 papers A 1B 1C 2Misc 1Journal 12Unranked 4
YearRankTypeTitle / Venue / Authors
2023 — conf
An Open-Source eFPGA-based SoC Design for Computation Acceleration.
ICECS
Yunus Emre Eryilmaz, Hasan Erdem Yantir, Müstak E. Yalçin
2023 J jnl
Architectural Trade-Off Analysis for Accelerating LSTM Network Using Radix-r OBC Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohd. Tasleem Khan, Hasan Erdem Yantir, Khaled Nabil Salama, Ahmed M. Eltawil
2022 J jnl
A hardware/software co-design methodology for in-memory processors.
J. Parallel Distributed Comput.
Hasan Erdem Yantir, Ahmed M. Eltawil, Khaled N. Salama
2022 J jnl
Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs.
IEEE Embed. Syst. Lett.
Muhammad Irfan, Hasan Erdem Yantir, Zahid Ullah, Ray C. C. Cheung
2022 J jnl
In-Memory Associative Processors: Tutorial, Potential, and Challenges.
IEEE Trans. Circuits Syst. II Express Briefs
Mohammed E. Fouda, Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
2022 J jnl
In-memory Associative Processors: Tutorial, Potential, and Challenges.
CoRR
Mohammed E. Fouda, Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
2022 J jnl
Toward the Optimal Design and FPGA Implementation of Spiking Neural Networks.
IEEE Trans. Neural Networks Learn. Syst.
Wenzhe Guo, Hasan Erdem Yantir, Mohammed E. Fouda, Ahmed M. Eltawil, Khaled Nabil Salama
2021 J jnl
IMCA: An Efficient In-Memory Convolution Accelerator.
IEEE Trans. Very Large Scale Integr. Syst.
Hasan Erdem Yantir, Ahmed M. Eltawil, Khaled N. Salama
2020 — conf
An Efficient 2D Discrete Cosine Transform Processor for Multimedia Applications.
SIU
Hasan Erdem Yantir, Ahmed M. Eltawil, Khaled N. Salama
2019 J jnl
Power Performance Tradeoffs Using Adaptive Bit Width Adjustments on Resistive Associative Processors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rana A. Abdelaal, Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
2018 J jnl
A Hybrid Approximate Computing Approach for Associative In-Memory Processors.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
2018 J jnl
A Two-Dimensional Associative Processor.
IEEE Trans. Very Large Scale Integr. Syst.
Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
2018 — —
Efficient Acceleration of Computation Using Associative In-memory Processing.
Hasan Erdem Yantir
2018 — conf
Low-Power Resistive Associative Processor Implementation Through the Multi-Compare.
ICECS
Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
2018 J jnl
Power optimization techniques for associative processors.
J. Syst. Archit.
Hasan Erdem Yantir, Ahmed M. Eltawil, Smaïl Niar, Fadi J. Kurdahi
2018 A conf
Rapid in-memory matrix multiplication using associative processor.
DATE
Mohamed Ayoub Neggaz, Hasan Erdem Yantir, Smaïl Niar, Ahmed M. Eltawil, Fadi J. Kurdahi
2017 J jnl
Approximate Memristive In-memory Computing.
ACM Trans. Embed. Comput. Syst.
Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi
2017 Misc conf
Efficient pulsed-latch implementation for multiport register files: work-in-progress.
CASES
Wael M. Elsharkasy, Hasan Erdem Yantir, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi
2016 C conf
Process variations-aware resistive associative processor design.
ICCD
Hasan Erdem Yantir, Mohammed E. Fouda, Ahmed M. Eltawil, Fadi J. Kurdahi
2014 — conf
An Efficient Heterogeneous Register File Implementation for FPGAs.
IPDPS Workshops
Hasan Erdem Yantir, Arda Yurdakul
2014 B conf
Application specific multi-port memory customization in FPGAs.
FPL
Gorker Alp Malazgirt, Hasan Erdem Yantir, Arda Yurdakul, Smaïl Niar
2013 C conf
Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAs.
DSD
Hasan Erdem Yantir, Salih Bayar, Arda Yurdakul