Haruki Mori - RankMe

21 papers C 1Journal 7Unranked 13

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm IEEE J. Solid State Circuits Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Kinshuk Khare, Brian Crafton, Hiroaki Ishii, Cheng-En Lee, Xiaochen Peng, Xiaoyu Sun, Yorinobu Fujino, Chia-Jung Tsen, Vineet Joshi, Chao-Kai Chuang, Takeshi Hashizume, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Hidehiro Fujiwara, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2026	J	`jnl`	Exploration of Algorithm-Hardware Co-Design for Floating-Point Digital Compute-in-Memory. IEEE Comput. Archit. Lett. Xiaochen Peng, Haruki Mori, Abhiroop Bhattacharjee, Brian Crafton, Hidehiro Fujiwara, Kerem Akarvardar
2026	J	`jnl`	Ultrafast Generative AI by Ultradense 3D Integration: A Case Study on LLM-based Edge Inference. ACM Trans. Design Autom. Electr. Syst. Kerem Akarvardar, Xiaoyu Sun, Brian Crafton, Xiaochen Peng, Haruki Mori, Abhiroop Bhattacharjee, Hidehiro Fujiwara, H.-S. Philip Wong
2025	J	`jnl`	Enhancing DCIM Efficiency with Multi-Storage-Row Architecture for Edge AI Workloads. IEEE Comput. Archit. Lett. Xiaoyu Sun, Haruki Mori, Wei-Chang Zhao, Je-Min Hung, Hidehiro Fujiwara, Brian Crafton, Bo Zhang, Win-San Khwa, Yu-Der Chih, Tsung-Yung Jonathan Chang, Kerem Akarvardar
2024	—	`conf`	20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices. ISSCC Ming-En Shih, Shih-Wei Hsieh, Ping-Yuan Tsai, Ming-Hung Lin, Pei-Kuei Tsung, En-Jui Chang, Jenwei Liang, Shu-Hsin Chang, Chung-Lun Huang, You-Yu Nian, Zhe Wan, Sushil Kumar, Cheng-Xin Xue, Gajanan Jedhe, Hidehiro Fujiwara, Haruki Mori, Chih-Wei Chen, Po-Hua Huang, Chih-Feng Juan, Chung-Yi Chen, Tsung-Yao Lin, Ch Wang, Chih-Cheng Chen, Kevin Jou
2024	—	`conf`	34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm ISSCC Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2024	J	`jnl`	Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaoyu Sun, Weidong Cao, Brian Crafton, Kerem Akarvardar, Haruki Mori, Hidehiro Fujiwara, Hiroki Noguchi, Yu-Der Chih, Meng-Fan Chang, Yih Wang, Tsung-Yung Jonathan Chang
2023	—	`conf`	A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. ISSCC Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2022	—	`conf`	A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications. VLSI Technology and Circuits Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang
2022	—	`conf`	A 5-nm 254-TOPS/W 221-TOPS/mm ISSCC Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2021	—	`conf`	An 89TOPS/W and 16.3TOPS/mm ISSCC Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Cheng Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang
2019	J	`jnl`	A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2018	—	`conf`	28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning. ICECS Haruki Mori, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2018	—	`conf`	Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning. SiPS Kazuki Yamada, Haruki Mori, Tetsuya Youkawa, Yuki Miyauchi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2018	—	`conf`	Delayed Weight Update for Faster Convergence in Data-Parallel Deep Learning. GlobalSIP Tetsuya Youkawa, Haruki Mori, Yuki Miyauchi, Kazuki Yamada, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2018	—	`conf`	Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth. ICECS Yuki Miyauchi, Haruki Mori, Tetsuya Youkawa, Kazuki Yamada, Shintato Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Atsuki Inoue
2017	—	`conf`	A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning. MLSP Haruki Mori, Tetsuya Youkawa, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Atsuki Inoue
2016	J	`jnl`	A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor. IEICE Trans. Electron. Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2016	—	`conf`	An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology. ICECS Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2015	—	`conf`	A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. CICC Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2015	C	`conf`	A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. ISCAS Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto