Haruhiko Ichino

17 papers C 1Journal 16

Year	Rank	Type	Title / Venue / Authors
2007	J	`jnl`	MAC protocol based on cross-layer design methodology for fast link in wireless communication systems. IEICE Electron. Express Shoko Ohteru, Keiji Kishine, Haruhiko Ichino
2005	J	`jnl`	Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks. IEICE Trans. Commun. Kazuhiko Terada, Kenji Kawai, Osamu Ishida, Keiji Kishine, Noboru Iwasaki, Haruhiko Ichino
2004	J	`jnl`	PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits. IEEE J. Solid State Circuits Keiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino
2002	J	`jnl`	Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX. IEEE J. Solid State Circuits Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino
2000	J	`jnl`	A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI. IEEE J. Solid State Circuits Kenji Kawai, Haruhiko Ichino
2000	C	`conf`	A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit. ISCAS Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino
1999	J	`jnl`	A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs. IEEE J. Solid State Circuits Keiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino
1999	J	`jnl`	A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design. IEEE J. Solid State Circuits Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino
1998	J	`jnl`	High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing. IEEE J. Solid State Circuits Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino
1997	J	`jnl`	A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic. IEEE J. Solid State Circuits Keiji Kishine, Yoshiji Kobayashi, Haruhiko Ichino
1995	J	`jnl`	Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops. IEEE J. Solid State Circuits Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi
1994	J	`jnl`	High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology. IEEE J. Solid State Circuits Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi
1994	J	`jnl`	Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit. IEEE J. Solid State Circuits Kiyoshi Ishii, Haruhiko Ichino, Chikara Yamaguchi
1993	J	`jnl`	20 Gb/s digital SSIs using AlGaAs/GaAs heterojunction bipolar transistors for future optical transmission systems. IEEE J. Solid State Circuits Haruhiko Ichino
1991	J	`jnl`	Comments on '18-GHz 1/8 dynamic frequency divider using Si bipolar technologies (and reply). IEEE J. Solid State Circuits Rainer H. Derksen, Haruhiko Ichino
1990	J	`jnl`	12-Gb/s decision circuit IC using AlGaAs/GaAS HBT technology. IEEE J. Solid State Circuits Haruhiko Ichino, Noboru Ishihara, Yoshiki Yamauchi, Osaake Nakajima, Koichi Nagata, Takumi Nittono
1989	J	`jnl`	18-GHz 1/8 dynamic frequency divider using Si bipolar technologies. IEEE J. Solid State Circuits Haruhiko Ichino, Noboru Ishihara, Masao Suzuki, Shinsuke Konaka