Harsh Rawat

11 papers C 2Misc 2Journal 2Unranked 5
YearRankTypeTitle / Venue / Authors
2025 C conf
AnalogSim: a Modeling Framework for SRAM-based Analog In-Memory Computing.
ISCAS
Talha Bin Aslam, Anuj Grover, Harsh Rawat
2023 — conf
A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications.
ISSCC
Giuseppe Desoli, Nitin Chawla, Thomas Boesch, Manui Avodhyawasi, Harsh Rawat, Hitesh Chawla, VS Abhijith, Paolo Zambotti, Akhilesh Sharma, Carmine Cappetta, Michele Rossi, Antonio De Vita, Francesca Girardi
2023 Misc conf
A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology.
VLSID
Belal Iqbal, Anuj Grover, Harsh Rawat
2022 C conf
3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS.
ISCAS
Mukesh Kumar Srivastav, Rimjhim, Roshan Mishra, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat
2022 — conf
A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators.
AICAS
Belal Iqbal, Anuj Grover, Harsh Rawat
2022 Misc conf
Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI.
VLSID
Chandan Kumar, Rahul Kumar, Anuj Grover, Shouri Chatterjee, Kedar Janardan Dhori, Harsh Rawat
2021 — conf
Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS.
ICECS
Mukesh Kumar Srivastav, Rimjhim, Govind Soni, Umang Mittal, Rupali Tewari, Riya Yadav, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat
2017 — conf
Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology.
SoCC
Harsh Rawat, K. Bharath, Alexander Fell
2015 — conf
A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI.
SoCC
Ramandeep Kaur, Alexander Fell, Harsh Rawat
2015 J jnl
FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Amit Chhabra, Harsh Rawat, Mohit Jain, Pascal Tessier, Daniel Pierredon, Laurent Bergher, Promod Kumar
2014 J jnl
Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Kedar Janardan Dhori, Vinay Kumar, Harsh Rawat