Harry Muljono

15 papers A 1Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2019 — conf
A 2.666GT/s 128GB/s 14nm Memory I/O with Jitter and Crosstalk Cancellation.
A-SSCC
Harry Muljono, Kathy Peng, Linda Sun, Isaac Abraham, Charlie Lin, Yanjie Zhu, Chunrong Song
2018 — conf
Augmenting ESD and EOS physical analysis with per pin ESD and leakage DFT.
ISQED
Horaira Abu, Salem Abdennadher, Benoit Provost, Harry Muljono
2018 — conf
SkyLake-SP: A 14nm 28-Core xeon® processor.
ISSCC
Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang
2015 J jnl
A 22 nm 15-Core Enterprise Xeon® Processor Family.
IEEE J. Solid State Circuits
Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang
2014 — conf
5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family.
ISSCC
Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang
2010 J jnl
A 45 nm 8-Core Enterprise Xeon¯ Processor.
IEEE J. Solid State Circuits
Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora
2009 — conf
A 45nm 8-core enterprise Xeon® processor.
ISSCC
Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli
2009 — conf
Power reduction techniques for an 8-core xeon® processor.
ESSCIRC
Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora
2007 J jnl
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.
IEEE J. Solid State Circuits
Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora
2006 — conf
A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache.
ISSCC
Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang
2004 A conf
AC IO Loopback Design for High Speed µProcessor IO Test.
ITC
Benoit Provost, Chee How Lim, Mo Bashir, Ali Muhtaroglu, Tiffany Huang, Kathy Tian, Mubeen Atha, Cangsang Zhao, Harry Muljono
2004 J jnl
Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache.
IEEE Micro
Stefan Rusu, Harry Muljono, Brian S. Cherkauer
2003 J jnl
A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache.
IEEE J. Solid State Circuits
Stefan Rusu, Jason Stinson, Simon Tam, Justin Leung, Harry Muljono, Brian S. Cherkauer
2003 J jnl
A 400-MT/s 6.4-GB/s multiprocessor bus interface.
IEEE J. Solid State Circuits
Harry Muljono, Beom-Taek Lee, Yanmei (Kathy) Tian, Yanbin (Eddie) Wang, Mubeen Atha, Tiffany Huang, Mitsuhiro Adachi, Stefan Rusu
2001 J jnl
Itanium
IEEE J. Solid State Circuits
Alper Ilkbahar, Srinivas Venkataraman, Harry Muljono