Harry Hsieh - RankMe

41 papers A* 5A 6Misc 2Journal 12Unranked 15

Year	Rank	Type	Title / Venue / Authors
2009	—	`conf`	Fast and accurate performance simulation of embedded software for MPSoC. ASP-DAC Eric Cheung, Harry Hsieh, Felice Balarin
2009	—	`conf`	Memory subsystem simulation in software TLM/T models. ASP-DAC Eric Cheung, Harry Hsieh, Felice Balarin
2009	—	`conf`	Partial order method for timed simulation of system-level MPSoC designs. ASP-DAC Eric Cheung, Harry Hsieh, Felice Balarin
2009	J	`jnl`	Runtime deadlock analysis for system level design. Des. Autom. Embed. Syst. Eric Cheung, Xi Chen, Harry Hsieh, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
2008	Misc	`conf`	Software optimization for MPSoC: a mpeg-2 decoder case study. CODES+ISSS Eric Cheung, Harry Hsieh, Felice Balarin
2007	J	`jnl`	Assertion-Based Design Exploration of DVS in Network Processor Architectures CoRR Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
2007	—	`conf`	Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip. HLDVT Eric Cheung, Harry Hsieh, Felice Balarin
2007	—	`conf`	Bridging RTL and gate: correlating different levels of abstraction for design debugging. HLDVT Eric Cheung, Xi Chen, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh
2007	—	`conf`	Framework for fast and accurate performance simulation of multiprocessor systems. HLDVT Eric Cheung, Harry Hsieh, Felice Balarin
2007	J	`jnl`	System Synthesis for Networks of Programmable Blocks CoRR Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid
2006	A	`conf`	Communication and co-simulation infrastructure for heterogeneous system integration. DATE Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli
2006	—	`conf`	Runtime Deadlock Analysis of SystemC Designs. HLDVT Eric Cheung, Piyush Satapathy, Vi Pham, Harry Hsieh, Xi Chen
2006	J	`jnl`	Verification Approach of Metropolis Design Framework for Embedded Systems. Int. J. Parallel Program. Xi Chen, Harry Hsieh, Felice Balarin
2005	A	`conf`	Assertion-Based Design Exploration of DVS in Network Processor Architectures. DATE Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
2005	A*	`conf`	Simulation based deadlock analysis for system level designs. DAC Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
2005	A	`conf`	System Synthesis for Networks of Programmable Blocks. DATE Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid
2005	—	`conf`	eBlocks - an enabling technology for basic sensor based systems. IPSN Susan Cotterell, Ryan Mannion, Frank Vahid, Harry Hsieh
2004	J	`jnl`	Assertion Based Verification and Analysis of Network Processor Architectures. Des. Autom. Embed. Syst. Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin
2004	—	`conf`	Assertion-based power/performance analysis of network processor architectures. HLDVT Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
2004	J	`jnl`	Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2004	A	`conf`	Utilizing Formal Assertions for System Design of Network Processors. DATE Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin
2003	A	`conf`	Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	A*	`conf`	Automatic trace analysis for logic of constraints. DAC Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	—	`conf`	Case Studies of Model Checking for Embedded System Designs. ACSD Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	Misc	`conf`	First results with eBlocks: embedded systems building blocks. CODES+ISSS Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh
2003	J	`jnl`	Formal Verification for Embedded System Designs. Des. Autom. Embed. Syst. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	J	`jnl`	Metropolis: An Integrated Electronic System Design Environment. Computer Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli
2003	—	`ch.`	Simulation Trace Verification for Quantitative Constraints. Embedded Software for SoC Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	—	`conf`	Verifying LOC based functional and performance constraints. HLDVT Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2002	—	`conf`	Formal verification of embedded system designs at multiple levels of abstraction. HLDVT Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2001	J	`jnl`	Synchronous approach to the functional equivalence of embeddedsystem implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
2000	A*	`conf`	Efficient methods for embedded system design space exploration. DAC Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
2000	—	`conf`	Refining abstract equivalence analysis for embedded system design. HLDVT Harry Hsieh, Felice Balarin
1999	A	`conf`	Synchronous equivalence for embedded systems: a tool for design exploration. ICCAD Harry Hsieh, Felice Balarin
1999	J	`jnl`	Synthesis of software programs for embedded control applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki
1997	—	`conf`	Modeling micro-controller peripherals for high-level co-simulation and synthesis. CODES Harry Hsieh, Alberto L. Sangiovanni-Vincentelli
1996	J	`jnl`	A case study in computer-aided co-design of embedded controllers. Des. Autom. Embed. Syst. Massimiliano Chiodo, Daniel W. Engels, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Kei Suzuki, Alberto L. Sangiovanni-Vincentelli
1996	A*	`conf`	Formal Verification of Embedded Systems based on CFSM Networks. DAC Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
1995	A*	`conf`	Synthesis of Software Programs for Embedded Control Applications. DAC Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Luciano Lavagno, Harry Hsieh, Kei Suzuki, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich
1994	—	`conf`	A case study in computer-aided codesign of embedded controllers. CODES Luciano Lavagno, Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Harry Hsieh, S. Yee, Alberto L. Sangiovanni-Vincentelli, Kei Suzuki
1994	J	`jnl`	Hardware-software codesign of embedded systems. IEEE Micro Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Luciano Lavagno