Haroon Waris

23 papers A* 1C 2Journal 15Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
Design and verification of a robust near-memory computing architecture for image fusion tasks.
Microelectron. J.
Aibin Yan, Han Bao, Jiaxun Cui, Haroon Waris, Jinpeng Li, Xiaoqing Wen
2026 J jnl
FPGA-Based Low-Power Signed Approximate Multipliers for Diverse Error-Resilient Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Yi Guo, XueTao Li, Xin Luo, Heming Sun, Haroon Waris, Weiqiang Liu
2025 J jnl
A Novel Error Metric for Evaluating the Error Correction Capability of Approximate Units.
IEEE Trans. Circuits Syst. II Express Briefs
Yuqin Dou, Zhikuang Cai, Haroon Waris, Roger F. Woods, Weiqiang Liu
2025 — conf
A Portable and Hybrid Verification Framework Using C and UVM for Secure RISC-V SoCs.
AsianHOST
Muhammad Yasir Farooq, Haroon Waris, Chenghua Wang, Muhammad Usman Akram, Jiatong Tian, Jiang Li, Weiqiang Liu
2025 J jnl
Low-Cost Yet Effective Trojan Mitigation Techniques for Approximate Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Zohaib Tariq, Haroon Waris, Rehan Ahmed, Yuqin Dou, Weiqiang Liu, Muhammad Imran
2025 A* conf
VEDA: Efficient LLM Generation Through Voting-based KV Cache Eviction and Dataflow-flexible Accelerator.
DAC
Zhican Wang, Hongxiang Fan, Haroon Waris, Gang Wang, Zhenyu Li, Jianfei Jiang, Yanan Sun, Guanghui He
2025 J jnl
VEDA: Efficient LLM Generation Through Voting-based KV Cache Eviction and Dataflow-flexible Accelerator.
CoRR
Zhican Wang, Hongxiang Fan, Haroon Waris, Gang Wang, Zhenyu Li, Jianfei Jiang, Yanan Sun, Guanghui He
2024 C conf
Design Co-Processor Based on Partially Homomorphic Encryption Execution Using Open-Source Tool.
VLSI-SoC
Mujahid Bilal, M. Kamran Bhatti, Muhammad Kahsif Minhas, Haroon Waris
2024 J jnl
FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuqin Dou, Chenghua Wang, Haroon Waris, Roger F. Woods, Weiqiang Liu
2024 C conf
FVDCLS: Functional Verification of RISCV Based Dual-Core Lockstep Feature Using Fault Injection Mechanism.
VLSI-SoC
Muhammad Kashif Minhas, Haroon Waris, Sajid Baloch
2023 J jnl
Approximate Softmax Functions for Energy-Efficient Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Ke Chen, Yue Gao, Haroon Waris, Weiqiang Liu, Fabrizio Lombardi
2023 J jnl
Exact and Approximate Squarers for Error-Tolerant Applications.
IEEE Trans. Computers
Ke Chen, Chenyu Xu, Haroon Waris, Weiqiang Liu, Paolo Montuschi, Fabrizio Lombardi
2022 — ch.
An Automated Logic-Level Framework for Approximate Modular Arithmetic Circuits.
Approximate Computing
Haroon Waris, Chenghua Wang, Weiqiang Liu
2022 — conf
Architectural-Space Exploration of Energy-Efficient Approximate Arithmetic Units for Error-Tolerant Applications.
ISVLSI
Haroon Waris, Chenghua Wang, Weiqiang Liu
2022 J jnl
AxRMs: Approximate Recursive Multipliers Using High-Performance Building Blocks.
IEEE Trans. Emerg. Top. Comput.
Haroon Waris, Chenghua Wang, Chenyu Xu, Weiqiang Liu
2022 J jnl
Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers.
IEEE Trans. Emerg. Top. Comput.
Haroon Waris, Chenghua Wang, Weiqiang Liu, Jie Han, Fabrizio Lombardi
2021 J jnl
AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs
Haroon Waris, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi
2021 J jnl
AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication.
J. Signal Process. Syst.
Haroon Waris, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi
2021 J jnl
Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning.
IEEE Trans. Sustain. Comput.
Peipei Yin, Chenghua Wang, Haroon Waris, Weiqiang Liu, Yinhe Han, Fabrizio Lombardi
2020 J jnl
Hybrid Low Radix Encoding-Based Approximate Booth Multipliers.
IEEE Trans. Circuits Syst.
Haroon Waris, Chenghua Wang, Weiqiang Liu
2019 — conf
Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication.
SiPS
Haroon Waris, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi
2019 J jnl
High-performance approximate half and full adder cells using NAND logic gate.
IEICE Electron. Express
Haroon Waris, Chenghua Wang, Weiqiang Liu
2018 — conf
Design Exploration of Small Bit-Width Multipliers Using Approximate Logic Design (ALD) Tool.
DSP
Haroon Waris, Weiqiang Liu, Pengfei Huang, Ruizhe Ma, Chenghua Wang, Fabrizio Lombardi