Harold Pilo - RankMe

13 papers A 2Journal 6Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection. IEEE Solid State Circuits Lett. Harold Pilo, Manish Arora, Chien-An Lai, Mike Lee, Zack Lo, Mayur Randeria
2025	—	`conf`	A 38Mb/mm ISSCC Harold Pilo, John Barth, Kapil Dev Dwivedi, Peter Lee, Vikram Kumar, Prasanna Nalawar, Yogeshbhai Patel, Shailendra Sharad, Shakti Singh
2013	—	`conf`	A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction. ISSCC Harold Pilo, Chad A. Adams, Igor Arsovski, Robert M. Houle, Steve Lamphier, Michael M. Lee, Frank Pavlik, Sushma N. Sambatur, Adnan Seferagic, Richard Wu, Mohammad Imran Younus
2012	J	`jnl`	A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. IEEE J. Solid State Circuits Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic
2011	—	`conf`	A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. ISSCC Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens
2009	J	`jnl`	An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management. IEEE J. Solid State Circuits Vinod Ramadurai, Harold Pilo, John Andersen, Geordie Braceras, John A. Gabric, Daniel Geise, Steve Lamphier, Yue Tan
2008	—	`conf`	A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management. ISSCC Harold Pilo, Vaidyanathan Ramadurai, Geordie Braceras, John A. Gabric, Steve Lamphier, Yue Tan
2007	—	`conf`	A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology. CICC Larry Wissel, Harold Pilo, Chris LeBlanc, Xiaopeng Wang, Steve Lamphier, Michael Fragano
2007	J	`jnl`	An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage. IEEE J. Solid State Circuits Harold Pilo, Charlie Barwin, Geordie Braceras, Chris Browning, Steve Lamphier, Fred Towler
2003	J	`jnl`	A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE J. Solid State Circuits Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier
2001	A	`conf`	Bitline contacts in high density SRAMs: design for testability and stressability. ITC Harold Pilo, R. Dean Adams, Robert E. Busch, Eric A. Nelson, Geoerge E. Rudgers
2000	J	`jnl`	An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin. IEEE J. Solid State Circuits Harold Pilo, Archie Allen, Jim Covino, Patrick Hansen, Steve Lamphier, Chris Murphy, Terry Traver, Pui Yee
2000	A	`conf`	Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond. ITC Harold Pilo, Stu Hall, Patrick Hansen, Steve Lamphier, Chris Murphy