Haris Javaid - RankMe

50 papers A* 7A 11B 2C 1Misc 3Journal 13Unranked 11

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Sparse Collectives: Exploiting Data Sparsity to Improve Communication Efficiency. NAIC Dhananjaya Wijerathne, Haris Javaid, Guanwen Zhong, Dan Wu, Xing Yuan Kom, Mario Baldi
2024	A	`conf`	SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators. DATE Jing Gong, Hassaan Saadat, Haris Javaid, Hasindu Gamaarachchi, David Taubman, Sri Parameswaran
2023	J	`jnl`	A Primer on RecoNIC: RDMA-enabled Compute Offloading on SmartNIC. CoRR Guanwen Zhong, Aditya Kolekar, Burin Amornpaisannon, Inho Choi, Haris Javaid, Mario Baldi
2023	J	`jnl`	ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jing Gong, Hassaan Saadat, Hasindu Gamaarachchi, Haris Javaid, Xiaobo Sharon Hu, Sri Parameswaran
2023	—	`conf`	Demo: Enabling DNN Inference in the Network Data Plane. EuroP4@CoNEXT Siddhartha, Justin Tan, Rajesh Bansal, Huang Chee Cheun, Yuta Tokusashi, Chong Yew Kwan, Haris Javaid, Mario Baldi
2022	J	`jnl`	ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference. CoRR Jing Gong, Hassaan Saadat, Hasindu Gamaarachchi, Haris Javaid, Xiaobo Sharon Hu, Sri Parameswaran
2022	A	`conf`	Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric. ICDCS Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan, Chengchen Hu, Gordon J. Brebner
2022	A	`conf`	Efficient FPGA-based ECDSA Verification Engine For Permissioned Blockchains. FPGA Rashmi Agrawal, Ji Yang, Haris Javaid
2022	—	`conf`	Efficient FPGA-based ECDSA Verification Engine for Permissioned Blockchains. ASAP Rashmi Agrawal, Ji Yang, Haris Javaid
2022	B	`conf`	Improving Energy Efficiency of Permissioned Blockchains Using FPGAs. ICPADS Nathania Santoso, Haris Javaid
2022	J	`jnl`	Improving Energy Efficiency of Permissioned Blockchains Using FPGAs. CoRR Nathania Santoso, Haris Javaid
2021	J	`jnl`	Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric. CoRR Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan, Chengchen Hu, Gordon J. Brebner
2021	J	`jnl`	Efficient FPGA-based ECDSA Verification Engine for Permissioned Blockchains. CoRR Rashmi Agrawal, Ji Yang, Haris Javaid
2020	Misc	`conf`	A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units. VLSID Hassaan Saadat, Tuo Li, Haris Javaid, Sri Parameswaran
2020	J	`jnl`	Hardware Trojan Mitigation in Pipelined MPSoCs. ACM Trans. Design Autom. Electr. Syst. Amin Malekpour, Roshan G. Ragel, Tuo Li, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2020	A	`conf`	REALM: Reduced-Error Approximate Log-based Integer Multiplier. DATE Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2020	—	`conf`	WEID: Worst-case Error Improvement in Approximate Dividers. ASP-DAC Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2019	A*	`conf`	Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias. DAC Hassaan Saadat, Haris Javaid, Sri Parameswaran
2019	—	`conf`	FastProxy: Hardware and Software Acceleration of Stratum Mining Proxy. CVCBT Guanwen Zhong, Haris Javaid, Hassaan Saadat, Lingchao Xu, Chengchen Hu, Gordon J. Brebner
2019	B	`conf`	Optimizing Validation Phase of Hyperledger Fabric. MASCOTS Haris Javaid, Chengchen Hu, Gordon J. Brebner
2019	J	`jnl`	Optimizing Validation Phase of Hyperledger Fabric. CoRR Haris Javaid, Chengchen Hu, Gordon J. Brebner
2016	J	`jnl`	Switchable cache: utilising dark silicon for application specific cache optimisations. IET Comput. Digit. Tech. Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Sri Parameswaran
2015	—	`conf`	ADAPT: An adaptive manycore methodology for software pipelined applications. ASP-DAC Xi Zhang, Haris Javaid, Muhammad Shafique, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran
2015	A	`conf`	E-pipeline: elastic hardware/software pipelines on a many-core fabric. DATE Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jörg Henkel, Sri Parameswaran
2015	J	`jnl`	Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Swarnalatha Radhakrishnan, Sri Parameswaran
2015	A	`conf`	Malleable NoC: dark silicon inspired adaptable Network-on-Chip. DATE Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran
2015	A*	`conf`	SuperNet: multimode interconnect architecture for manycore chips. DAC Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran
2014	J	`jnl`	Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran
2014	A*	`conf`	FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs. DAC Haris Javaid, Yusuke Yachide, Su Myat Min Shwe, Haseeb Bokhari, Sri Parameswaran
2014	A	`conf`	Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs. DATE Hong Chinh Doan, Haris Javaid, Sri Parameswaran
2014	A	`conf`	Hardware-based fast exploration of cache hierarchies in application specific MPSoCs. DATE Isuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran
2014	J	`jnl`	Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs). IEEE Trans. Parallel Distributed Syst. Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2014	—	`book`	Pipelined Multiprocessor System-on-Chip for Multimedia. Haris Javaid, Sri Parameswaran
2014	A*	`conf`	darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon. DAC Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran
2013	—	`conf`	A case study on exploration of last-level cache for energy reduction in DDR3 DRAM. MECO Su Myat Min, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2013	C	`conf`	Energy-aware synthesis of application specific MPSoCs. ICCD Thannirmalai Somu Muthukaruppan, Haris Javaid, Tulika Mitra, Sri Parameswaran
2013	—	`conf`	Multi-mode pipelined MPSoCs for streaming applications. ASP-DAC Haris Javaid, Daniel Witono, Sri Parameswaran
2013	—	`conf`	RExCache: Rapid exploration of unified last-level cache. ASP-DAC Su Myat Min, Haris Javaid, Sri Parameswaran
2013	—	`conf`	System-level optimization of on-chip communication using express links for throughput constrained MPSoCs. ESTIMedia Haseeb Bokhari, Haris Javaid, Sri Parameswaran
2013	A*	`conf`	XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs. DAC Su Myat Min, Haris Javaid, Sri Parameswaran
2012	—	`—`	Analyses and Optimisations for Pipelined MPSoCs. Haris Javaid
2011	A*	`conf`	Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study. DAC Haris Javaid, Muhammad Shafique, Sri Parameswaran, Jörg Henkel
2011	—	`conf`	Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos. ESTIMedia Hong Chinh Doan, Haris Javaid, Sri Parameswaran
2011	A	`conf`	System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia. ICCAD Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran
2010	A	`conf`	Fidelity metrics for estimation models. ICCAD Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2010	Misc	`conf`	Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications. CODES+ISSS Haris Javaid, Xin He, Aleksandar Ignjatovic, Sri Parameswaran
2010	J	`jnl`	Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2010	A	`conf`	Rapid runtime estimation methods for pipelined MPSoCs. DATE Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran
2009	A*	`conf`	A design flow for application specific heterogeneous pipelined multiprocessor systems. DAC Haris Javaid, Sri Parameswaran
2008	Misc	`conf`	Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. CODES+ISSS Haris Javaid, Sri Parameswaran