Harika Manem

15 papers C 1Misc 1Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2018 J jnl
Design Considerations for Memristive Crossbar Physical Unclonable Functions.
ACM J. Emerg. Technol. Comput. Syst.
Mesbah Uddin, Md. Badruddoja Majumder, Karsten Beckmann, Harika Manem, Zahiruddin Alamgir, Nathaniel C. Cady, Garrett S. Rose
2017 J jnl
Performance Enhancement of a Time-Delay PUF Design by Utilizing Integrated Nanoscale ReRAM Devices.
IEEE Trans. Emerg. Top. Comput.
Karsten Beckmann, Harika Manem, Nathaniel C. Cady
2016 — conf
Techniques for Improved Reliability in Memristive Crossbar PUF Circuits.
ISVLSI
Mesbah Uddin, Md. Badruddoja Majumder, Garrett S. Rose, Karsten Beckmann, Harika Manem, Zahiruddin Alamgir, Nathaniel C. Cady
2015 — conf
An extendable multi-purpose 3D neuromorphic fabric using nanoscale memristors.
CISDA
Harika Manem, Karsten Beckmann, Min Xu, Robert Carroll, Robert E. Geer, Nathaniel C. Cady
2012 J jnl
An Energy-Efficient Memristive Threshold Logic Circuit.
IEEE Trans. Computers
Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose
2012 J jnl
Design Considerations for Multilevel CMOS/Nano Memristive Memory.
ACM J. Emerg. Technol. Comput. Syst.
Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose
2012 J jnl
Leveraging Memristive Systems in the Construction of Digital Logic Circuits.
Proc. IEEE
Garrett S. Rose, Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Robinson E. Pino
2012 J jnl
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array.
IEEE Trans. Circuits Syst. I Regul. Pap.
Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose
2011 C conf
A read-monitored write circuit for 1T1M multi-level memristor memories.
ISCAS
Harika Manem, Garrett S. Rose
2011 Misc conf
An Approach to Tolerate Process Related Variations in Memristor-Based Applications.
VLSI Design
Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose
2010 — conf
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory.
ACM Great Lakes Symposium on VLSI
Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang
2010 — conf
Memristor based programmable threshold logic array.
NANOARCH
Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose
2009 J jnl
Inversion schemes for sublithographic programmable logic arrays.
IET Comput. Digit. Tech.
Benjamin Gojman, Harika Manem, Garrett S. Rose, André DeHon
2009 — conf
The effects of logic partitioning in a majority logic based CMOS-NANO FPGA.
ACM Great Lakes Symposium on VLSI
Harika Manem, Garrett S. Rose
2008 — conf
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays.
ACM Great Lakes Symposium on VLSI
Harika Manem, Peter C. Paliwoda, Garrett S. Rose