Harijot Singh Bindra

17 papers C 2Journal 7Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 0.4-0.9 V Supply Voltage-Flexible Third-Order Passive ΔΣ Modulator With Switched-Capacitor Loop Filter Achieving 71.9 dB Peak SNDR at 4 MHz Bandwidth.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jeroen Ponte, Harijot Singh Bindra, Bram Nauta
2025 J jnl
A 12.8-GS/s Time-Interleaved Sub-Sampling ADC Front End With 38-GHz Input Bandwidth and >39-dB SNDR for 1-32 GHz in 22-nm FDSOI.
IEEE J. Solid State Circuits
Josef Heel, Harijot Singh Bindra, Simon M. Louwsma, Alessandro Dezzani, Bram Nauta
2025 — conf
A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI.
ISSCC
Josef Heel, Harijot Singh Bindra, Simon M. Louwsma, Alessandro Dezzani, Bram Nauta
2025 J jnl
A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection.
IEEE J. Solid State Circuits
Viswesh Kendae Ramkumar, Maikel Huiskamp, Harijot Singh Bindra, Eric A. M. Klumperink, Bram Nauta
2025 C conf
Dynamic-Window DAC Switching in SAR ADCs and its Mismatch Modelling for High Peak-to-Average Ratio Input Signals.
ISCAS
A. K. Rajendra, J. Freriksen, Harijot Singh Bindra
2025 — conf
Time Modulated Array and Time Variant Filter Techniques to Reduce Receiver Hardware Complexity and Power Consumption.
EuCNC/6G Summit
Viswesh Kendae Ramkumar, Harijot Singh Bindra, Eric A. M. Klumperink, Basem Abdelaziz Abdelmagid, H. Wang
2023 J jnl
A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation.
IEEE Trans. Circuits Syst. II Express Briefs
Yuting Shen, Hanyue Li, Harijot Singh Bindra, Eugenio Cantatore, Pieter Harpe
2022 — conf
A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch.
ISSCC
Harijot Singh Bindra, Jeroen Ponte, Bram Nauta
2022 J jnl
Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates.
IEEE Trans. Circuits Syst. I Regul. Pap.
Maikel Huiskamp, Mark S. Oude Alink, Bram Nauta, Anne-Johan Annema, Harijot Singh Bindra
2021 J jnl
Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging.
IEEE J. Solid State Circuits
Joeri Lechevallier, Harijot Singh Bindra, Ronan A. R. van der Zee, Bram Nauta
2019 — conf
A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator.
VLSI Circuits
Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta
2019 — conf
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply.
CICC
Harijot Singh Bindra, Anne-Johan Annema, Gerard Wienk, Bram Nauta, Simon M. Louwsma
2018 J jnl
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.
IEEE J. Solid State Circuits
Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta
2017 — conf
A 30fJ/comparison dynamic bias comparator.
ESSCIRC
Harijot Singh Bindra, Chris E. Lokin, Anne-Johan Annema, Bram Nauta
2017 — conf
An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC.
ESSCIRC
Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Ed J. M. van Tuijl, Bram Nauta
2017 — conf
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs.
A-SSCC
Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta
2013 C conf
Clock and data recovery module in 90nm for 10Gbps serial link with -18dB channel attenuation.
ISCAS
Harijot Singh Bindra, Shouri Chatterjee, Kaushik Saha, Taranjit Kukal