Haridimos T. Vergos

69 papers A 1C 10Misc 2Journal 25Unranked 31

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Efficient modulo 2 ISVLSI Dimitris Bakalis, Haridimos T. Vergos
2016	—	`conf`	Extending the viability of power signature - Based IP watermarking in the SoC era. ICECS George Blanas, Haridimos T. Vergos
2015	J	`jnl`	Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators. Circuits Syst. Signal Process. Haridimos T. Vergos, Dimitris Bakalis, A. Anastasiou
2014	—	`conf`	Easily verified IP watermarking. DTIS Anastasios N. Bikos, Haridimos T. Vergos
2013	—	`conf`	Fast parallel-prefix Ling-carry adders in QCA nanotechnology. ICECS Alexios Thanos, Haridimos T. Vergos
2013	—	`conf`	RNS assisted image filtering and edge detection. DSP Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2013	—	`conf`	Reverse converters for RNSs with diminished-one encoded channels. EUROCON Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2012	J	`jnl`	Area-time efficient end-around inverted carry adders. Integr. Haridimos T. Vergos
2012	J	`jnl`	Area-time efficient multi-modulus adders and their applications. Microprocess. Microsystems Haridimos T. Vergos, Dimitris Bakalis
2012	J	`jnl`	On Modulo 2^n+1 Adder Design. IEEE Trans. Computers Haridimos T. Vergos, Giorgos Dimitrakopoulos
2012	C	`conf`	SUT-RNS Residue-to-Binary Converters Design. DSD Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2011	J	`jnl`	Efficient modulo 2 Integr. Dimitris Bakalis, Haridimos T. Vergos, Anastasia Spyrou
2011	C	`conf`	Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion. DSD Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2011	J	`jnl`	On the Design of Modulo 2 Circuits Syst. Signal Process. Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2011	—	`conf`	On the use of double-LSB and signed-LSB encodings for RNS. DSP Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2010	—	`conf`	A Family of Area-Time Efficient Modulo 2n+1 Adders. ISVLSI Haridimos T. Vergos
2010	C	`conf`	Area-Efficient Multi-moduli Squarers for RNS. DSD Dimitris Bakalis, Haridimos T. Vergos
2010	J	`jnl`	Fast modulo 2 Integr. Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou
2010	J	`jnl`	On Implementing Efficient Modulo 2 J. Circuits Syst. Comput. Haridimos T. Vergos, Dimitris Bakalis
2010	—	`conf`	SUT-RNS Forward and Reverse Converters. ISVLSI Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2010	—	`conf`	SUT-RNS Forward and Reverse Converters. ISVLSI (Selected papers) Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2009	—	`conf`	Efficient architectures for modulo 2n-1 squares. DPS Anastasia Spyrou, Dimitris Bakalis, Haridimos T. Vergos
2009	J	`jnl`	Efficient modulo 2 Integr. Haridimos T. Vergos, Costas Efstathiou
2009	—	`conf`	Novel modulo 2n+1 subtractors. DPS Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2008	J	`jnl`	A Unifying Approach for Weighted and Diminished-1 Modulo 2 IEEE Trans. Circuits Syst. II Express Briefs Haridimos T. Vergos, Costas Efstathiou
2008	—	`conf`	Efficient modulo 2 ICECS Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou
2008	C	`conf`	On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. DSD Haridimos T. Vergos, Dimitris Bakalis
2007	C	`conf`	An Efficient BIST Scheme for Non-Restoring Array Dividers. DSD Haridimos T. Vergos
2007	J	`jnl`	Design of efficient modulo 2 IET Comput. Digit. Tech. Haridimos T. Vergos, Costas Efstathiou
2007	J	`jnl`	RNS multiplication/sum-of-squares units. IET Comput. Digit. Tech. D. Adamidis, Haridimos T. Vergos
2006	J	`jnl`	A core generator for arithmetic cores and testing structures with a network interface. J. Syst. Archit. Dimitris Bakalis, Kostas Adaos, Dimitrios Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos
2006	C	`conf`	Novel Modulo 2 DSD Haridimos T. Vergos, Costas Efstathiou
2005	J	`jnl`	Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
2005	C	`conf`	KoVer: A Sophisticated Residue Arithmetic Core Generator. IEEE International Workshop on Rapid System Prototyping Nikolaos Kostaras, Haridimos T. Vergos
2005	—	`conf`	Modulo 2 ECCTD D. Adamidis, Haridimos T. Vergos
2005	—	`conf`	New architectures for modulo 2N - 1 adders. ICECS Giorgos Dimitrakopoulos, Dimitris G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2005	J	`jnl`	On the Design of Efficient Modular Adders. J. Circuits Syst. Comput. Haridimos T. Vergos, Costas Efstathiou
2004	C	`conf`	Diminished-1 Modulo 2 DSD Haridimos T. Vergos, Costas Efstathiou
2004	J	`jnl`	Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2004	J	`jnl`	Modified Booth Modulo 2 IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2003	—	`conf`	A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2003	—	`conf`	A systematic methodology for designing area-time efficient parallel-prefix modulo 2 ISCAS (5) Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2003	C	`conf`	An Efficient BIST scheme for High-Speed Adders. IOLTS Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
2003	J	`jnl`	Deterministic BIST for RNS Adders. IEEE Trans. Computers Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
2003	—	`conf`	Efficient BIST schemes for RNS datapaths. ISCAS (5) Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
2003	—	`conf`	Efficient modulo 2 ICECS Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
2003	J	`jnl`	Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2002	J	`jnl`	Diminished-One Modulo 2 IEEE Trans. Computers Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos
2002	—	`conf`	Ling adders in CMOS standard cell technologies. ICECS Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2002	J	`jnl`	On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. J. Syst. Archit. Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou
2001	—	`conf`	A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
2001	C	`conf`	High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2001	J	`jnl`	Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. VLSI Design Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou
2001	—	`conf`	On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos
2001	—	`conf`	On the design of modulo 2 ICECS Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2000	J	`jnl`	High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos
2000	—	`conf`	Low Power BIST for Wallace Tree-Based Fast Multipliers. ISQED Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos
2000	—	`conf`	Modified Booth 1's complement and modulo 2 ICECS Costas Efstathiou, Haridimos T. Vergos
1999	—	`conf`	Design and Analysis of On-Chip CPU Pipelined Caches. VLSI C. Ninos, Haridimos T. Vergos, Dimitris Nikolos
1999	—	`conf`	Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. Asian Test Symposium G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos
1999	—	`conf`	Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou
1999	—	`conf`	On Path Delay Fault Testing of Multiplexer - Based Shifters. Great Lakes Symposium on VLSI Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis
1999	J	`jnl`	On the Yield of VLSI Processors with On-Chip CPU Cache. IEEE Trans. Computers Dimitris Nikolos, Haridimos T. Vergos
1999	A	`conf`	Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. DATE Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas
1999	Misc	`conf`	Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. EDCC Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos
1999	—	`conf`	Path delay fault testing of Benes multistage interconnection networks. ICECS Haridimos T. Vergos, Maciej Bellos, Dimitris Nikolos
1996	Misc	`conf`	On the Yield of VLSI Processors with on-chip CPU Cache. EDCC Dimitris Nikolos, Haridimos T. Vergos
1996	—	`conf`	Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches. DFT Dimitris Nikolos, Haridimos T. Vergos, Antonis Vazaios, Spyros Voulgaris
1995	J	`jnl`	Efficient fault tolerant cache memory design. Microprocess. Microprogramming Haridimos T. Vergos, Dimitris Nikolos