Haram Ju

21 papers C 2Journal 12Unranked 7
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 1.19-pJ/b 32-Gb/s Baud-Rate Receiver Employing 2UI Integrated Pattern-Based CDR and DFE Adaptation Without Data-Level Reference.
IEEE J. Solid State Circuits
Suil Kang, Sinho Lee, Young-Wook Kim, Junhak Kim, Ho-Joon Shin, Haram Ju, Kwangho Lee, Kwanseo Park
2025 J jnl
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sinho Lee, Daeun Yun, Junhak Kim, Suil Kang, Young-Wook Kim, Kwangho Lee, Haram Ju, Sanghee Lee, Kwanseo Park
2023 J jnl
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS.
IEEE J. Solid State Circuits
Woosong Jung, Kwangho Lee, Kwanseo Park, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong
2022 J jnl
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector.
IEEE J. Solid State Circuits
Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog-Kyoon Jeong
2021 — conf
A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS.
A-SSCC
Kwangho Lee, Woosong Jung, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong
2021 — conf
A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS.
A-SSCC
Haram Ju, Kwangho Lee, Woosong Jung, Deog-Kyoon Jeong
2021 J jnl
An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Kwangho Lee, Hyojun Kim, Woosong Jung, Jinhyung Lee, Haram Ju, Kwanseo Park, Ook Kim, Deog-Kyoon Jeong
2020 J jnl
A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation.
IEEE Trans. Very Large Scale Integr. Syst.
Hye-Yoon Joo, Jinhyung Lee, Haram Ju, Han-Gon Ko, Jungmin Yoon, Byungjun Kang, Deog-Kyoon Jeong
2019 J jnl
A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver.
IEEE Trans. Circuits Syst. II Express Briefs
Moon-Chul Choi, Deog-Kyoon Jeong, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko, Haram Ju, Kwanseo Park, Hyojun Kim, Kwandong Kim
2019 — conf
A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS.
ICEIC
Moon-Chul Choi, Haram Ju, Han-Gon Ko, Deog-Kyoon Jeong
2019 J jnl
A Modulo-FIR Equalizer for Wireline Communications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gyu-Seob Jeong, Byungjun Kang, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong
2018 — conf
A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS.
VLSI Circuits
Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Deog-Kyoon Jeong
2018 J jnl
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards.
IEEE Trans. Ind. Electron.
Woo-Rham Bae, Haram Ju, Kwanseo Park, Jaeduk Han, Deog-Kyoon Jeong
2017 J jnl
A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G
IEEE Trans. Circuits Syst. II Express Briefs
Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong
2016 J jnl
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G
IEEE J. Solid State Circuits
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2016 — conf
A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS.
A-SSCC
Woo-Rham Bae, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong
2016 J jnl
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS.
IEEE J. Solid State Circuits
Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong
2016 C conf
A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme.
ISCAS
Haram Ju, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2015 C conf
A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.
ISCAS
Kwanseo Park, Woo-Rham Bae, Haram Ju, Jinhyung Lee, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
2015 — conf
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.
A-SSCC
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2015 — conf
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS.
A-SSCC
Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong