Harald Michalik

37 papers A 1B 1C 2Misc 1Journal 2Unranked 29

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	A Framework for Fault Tolerance in RISC-V. DASC/PiCom/CBDCom/CyberSciTech Alexander Dörflinger, Benedikt Kleinbeck, Mark Albers, Harald Michalik, Martin Moya
2021	—	`conf`	A comparative survey of open-source application-class RISC-V processor implementations. CF Alexander Dörflinger, Mark Albers, Benedikt Kleinbeck, Yejun Guan, Harald Michalik, Raphael Klink, Christopher Blochwitz, Anouar Nechi, Mladen Berekovic
2020	—	`conf`	ECC Memory for Fault Tolerant RISC-V Processors. ARCS Alexander Dörflinger, Yejun Guan, Sören Michalik, Sönke Michalik, Jamin Naghmouchi, Harald Michalik
2019	—	`conf`	Demonstrating Controlled Change for Autonomous Space Vehicles. AHS Alexander Dörflinger, Mark Albers, Björn Fiethe, Harald Michalik, Mischa Möstl, Johannes Schlatow, Rolf Ernst
2019	—	`conf`	Self-Adaptation for Availability in CPU-FPGA Systems Under Soft Errors. AHS Mischa Möstl, Alexander Dörflinger, Mark Albers, Harald Michalik, Rolf Ernst
2018	—	`conf`	Electronic Automotive and Aerospace Systems - a Master Programme on electronics design for safety critical applications. EWME Harald Michalik, Holger Dinse
2018	—	`conf`	Hardware Acceleration in Genode OS Using Dynamic Partial Reconfiguration. ARCS Alexander Dörflinger, Mark Albers, Björn Fiethe, Harald Michalik
2018	—	`conf`	Hardware and Software Task Scheduling for ARM-FPGA Platforms. AHS Alexander Dörflinger, Mark Albers, Johannes Schlatow, Björn Fiethe, Harald Michalik, Phillip Keldenich, Sándor P. Fekete
2017	—	`conf`	On-board processing using reconfigurable hardware on the solar orbiter PHI instrument. AHS Tobias Lange, Björn Fiethe, Holger Michel, Harald Michalik, Kinga Albert, Johann Hirzberger
2017	—	`conf`	Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments. AHS Alexander Dörflinger, Björn Fiethe, Harald Michalik, Sándor P. Fekete, Phillip Keldenich, Christian Scheffer
2017	—	`conf`	SEU fault classification by fault injection for an FPGA in the space instrument SOPHI. AHS Holger Michel, Hipólito Guzmán-Miranda, Alexander Dörflinger, Harald Michalik, Miguel Aguirre Aguirre Echánove
2015	—	`conf`	Read back scrubbing for SRAM FPGAs in a data processing unit for space instruments. AHS Holger Michel, Adrian Belger, Tobias Lange, Björn Fiethe, Harald Michalik
2014	C	`conf`	Dependable reconfigurable space systems: Challenges, new trends and case studies. IOLTS Antonis M. Paschalis, Harald Michalik, Nektarios Kranitis, Celia López-Ongil, Pedro Reviriego Vasallo
2014	—	`conf`	Efficient reconfiguration of processing modules on FPGAs for space instruments. AHS Sándor P. Fekete, Björn Fiethe, Stephan Friedrichs, Harald Michalik, Christos Orlis
2013	—	`conf`	Reconfigurable platforms for Data Processing on scientific space instruments. AHS Frank Bubenhagen, Björn Fiethe, Tobias Lange, Harald Michalik, Holger Michel
2013	—	`conf`	Worst case error rate predictions and mitigation schemes for Virtex-4 FPGAs on solar orbiter. AHS Holger Michel, Frank Bubenhagen, Kai Grurmann, Tobias Lange, Björn Fiethe, Harald Michalik
2012	—	`conf`	Adaptive hardware by dynamic reconfiguration for the Solar Orbiter PHI instrument. AHS Björn Fiethe, Frank Bubenhagen, Tobias Lange, Harald Michalik, Holger Michel, Joachim Woch, Johann Hirzberger
2012	—	`conf`	Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs. ARC Gang Zhou, Li Li, Harald Michalik
2012	—	`conf`	Institut für Datentechnik und Kommunikationsnetze - Mitgestaltung der Informatik in Braunschweig. 40 Jahre Informatik @ Braunschweig Rolf Ernst, Harald Michalik, Peter Rüffer
2012	—	`conf`	The SoCWire protocol (SoCP): A flexible and minimal protocol for a Network-on-Chip. AHS Holger Michel, Adrian Belger, Frank Bubenhagen, Björn Fiethe, Harald Michalik, Wayne Sullivan, Alex Wishart, Jørgen Ilstad
2011	—	`ch.`	A Communication Architecture for Distributed Real-Time Robot Control. Robotic Systems for Handling and Assembly Yannick Dadji, Harald Michalik, Nnamdi Kohn, Jens Steiner, Guido Beckmann, Tobias Möglich, J. Uwe Varchmin
2011	—	`conf`	AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit. AHS Holger Michel, Frank Bubenhagen, Björn Fiethe, Harald Michalik, Björn Osterloh, Wayne Sullivan, Alex Wishart, Jørgen Ilstad, Sandi Habinc
2010	—	`conf`	Architecture verification of the SoCWire NoC approach for safe dynamic partial reconfiguration in space applications. AHS Björn Osterloh, Harald Michalik, Björn Fiethe, Frank Bubenhagen
2010	J	`jnl`	Comments on "A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Field". IEEE Trans. Computers Gang Zhou, Harald Michalik
2010	J	`jnl`	Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Gang Zhou, Harald Michalik, László Hinsenkamp
2009	—	`conf`	Dynamic Partial Reconfiguration in Space Applications. AHS Björn Osterloh, Harald Michalik, Sandi Habinc, Björn Fiethe
2009	—	`conf`	Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs. ARC Gang Zhou, Harald Michalik, László Hinsenkamp
2009	Misc	`conf`	Parallel Architecture For Real Time Control System Based On The IEEE1394 Standard. PDPTA Yannick Dadji Foyet, Harald Michalik, Tobias Möglich
2009	—	`conf`	SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs. ARCS Björn Osterloh, Harald Michalik, Björn Fiethe
2008	B	`conf`	Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS. FPL Gang Zhou, Li Li, Harald Michalik
2008	—	`conf`	Networked Architecture for Distributed PC-based Robot Control Systems. ARCS Yannick Dadji, Jochen Maaß, Harald Michalik, Tobias Möglich, Nnamdi Kohn, J. Uwe Varchmin
2008	—	`conf`	SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications. AHS Björn Osterloh, Harald Michalik, Björn Fiethe, Karel Kotarowski
2007	—	`conf`	Efficient and High-Throughput Implementations of AES-GCM on FPGAs. FPT Gang Zhou, Harald Michalik, László Hinsenkamp
2007	—	`conf`	Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application. AHS Björn Osterloh, Harald Michalik, Björn Fiethe, Frank Bubenhagen
2007	A	`conf`	Reconfigurable system-on-chip data processing units for space imaging instruments. DATE Björn Fiethe, Harald Michalik, C. Dierker, Björn Osterloh, Gang Zhou
2004	C	`conf`	Image data compressor for Huygens' DISR instrument compared to state of the art compression schemes. IGARSS Peter Rueffer, Harald Michalik, Fritz Gliem, Frank Rabe
1986	—	`conf`	Der Instrumentenrechner der Halley Multicolour Camera. ARCS E. Krahn, Fritz Gliem, Harald Michalik, Peter Rüffer