Haralampos-G. D. Stratigopoulos

93 papers A* 2A 19B 9C 8Misc 16Journal 27Unranked 12

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	Analog and Mixed-Signal IC Security via Sizing Camouflaging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Julian Leonhard, Alhassan Sayed, Marie-Minerve Louërat, Hassan Aboushady, Haralampos-G. D. Stratigopoulos
2021	—	`conf`	Breaking Analog Biasing Locking Techniques via Re-Synthesis. ASP-DAC Julian Leonhard, Mohamed Elshamy, Marie-Minerve Louërat, Haralampos-G. D. Stratigopoulos
2020	B	`conf`	Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism. ETS Mohamed Elshamy, Giorgio Di Natale, Antonios Pavlidis, Marie-Minerve Louërat, Haralampos-G. D. Stratigopoulos
2020	A	`conf`	Securing Programmable Analog ICs Against Piracy. DATE Mohamed Elshamy, Alhassan Sayed, Marie-Minerve Louërat, Amine Rhouni, Hassan Aboushady, Haralampos-G. D. Stratigopoulos
2020	C	`conf`	Spiking Neuron Hardware-Level Fault Modeling. IOLTS Sarah A. El-Sayed, Theofilos Spyrou, Antonios Pavlidis, Engin Afacan, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. D. Stratigopoulos
2020	A	`conf`	Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP. DATE Antonios Pavlidis, Marie-Minerve Louërat, Eric Faehn, Anand Kumar, Haralampos-G. D. Stratigopoulos
2019	Misc	`conf`	IP Session on Machine Learning Applications in IC Test-Related Tasks. VTS Ghada Sokar, Yassin Zakaria, Asmaa Rabie, Kareem Madkour, Ira Leventhal, Jochen Rivoir, Xinli Gu, Haralampos-G. D. Stratigopoulos
2019	A	`conf`	MixLock: Securing Mixed-Signal Circuits via Logic Locking. DATE Julian Leonhard, Muhammad Yasin, Shadi Turk, Mohammed Thari Nabeel, Marie-Minerve Louërat, Roselyne Chotin-Avot, Hassan Aboushady, Ozgur Sinanoglu, Haralampos-G. D. Stratigopoulos
2019	—	`conf`	Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application. SMACD Julian Leonhard, Marie-Minerve Louërat, Hassan Aboushady, Ozgur Sinanoglu, Haralampos-G. D. Stratigopoulos
2019	—	`conf`	Self-Testing Analog Spiking Neuron Circuit. SMACD Sarah A. El-Sayed, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. D. Stratigopoulos
2018	J	`jnl`	Adaptive Test With Test Escape Estimation for Mixed-Signal ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haralampos-G. D. Stratigopoulos, Christian Streitwieser
2018	B	`conf`	Machine learning applications in IC testing. ETS Haralampos-G. D. Stratigopoulos
2018	C	`conf`	Open Source Hardware and EDA Tools for Analog/Mixed-Signal Design and Prototyping. ISCAS Naohiko Shimizu, Junichi Akita, Marie-Minerve Louërat, Haralampos-G. D. Stratigopoulos, Jean-Paul Chaput, Dimitri Galayko
2018	Misc	`conf`	Special session on machine learning: How will machine learning transform test? VTS Yiorgos Makris, Amit Nahar, Haralampos-G. D. Stratigopoulos, Marc Hutner
2017	Misc	`conf`	Adaptive test flow for mixed-signal ICs. VTS Haralampos-G. D. Stratigopoulos, Christian Streitwieser
2017	B	`conf`	Foreword. ETS Maria K. Michael, Rolf Drechsler, Stephan Eggersglüß, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken
2017	J	`jnl`	Recap of the European Test Symposium 2017 (ETS'17). IEEE Des. Test Maria K. Michael, Haralampos-G. D. Stratigopoulos
2017	J	`jnl`	Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ali Ahmadi, Haralampos-G. D. Stratigopoulos, Ke Huang, Amit Nahar, Bob Orr, Michael Pas, John M. Carulli, Yiorgos Makris
2016	J	`jnl`	A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electron. Test. Guillaume Renaud, Manuel J. Barragán, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet
2016	J	`jnl`	A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Manuel J. Barragán, Rshdee Alhakim, Haralampos-G. D. Stratigopoulos, Matthieu Dubois, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
2016	A	`conf`	Built-in test of millimeter-Wave circuits based on non-intrusive sensors. DATE Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld
2016	B	`conf`	ETS 2016 foreword. ETS Said Hamdioui, Giorgio Di Natale, Bram Kruseman, Maria K. Michael, Haralampos-G. D. Stratigopoulos
2016	J	`jnl`	Guest Editors' Introduction: Top Papers from the 2015 International Test Conference. IEEE Des. Test Nicola Nicolici, Haralampos-G. D. Stratigopoulos
2016	C	`conf`	Harnessing fabrication process signature for predicting yield across designs. ISCAS Ali Ahmadi, Haralampos-G. D. Stratigopoulos, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris
2016	J	`jnl`	One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Martin Andraud, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu
2016	J	`jnl`	Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. IEEE Des. Test Manuel J. Barragán, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
2015	A	`conf`	Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. ITC Haralampos-G. D. Stratigopoulos, Manuel J. Barragán, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
2015	J	`jnl`	Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique. IEEE Trans. Circuits Syst. I Regul. Pap. Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet
2015	A	`conf`	Fast deployment of alternate analog test using Bayesian model fusion. DATE John Liaperdos, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni, Xin Li
2015	B	`conf`	High frequency jitter estimator for SoCs. ETS Hervé Le Gall, Rshdee Alhakim, Miroslav Valka, Salvador Mir, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu
2015	J	`jnl`	Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors. J. Electron. Test. Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld
2015	—	`conf`	Test and Calibration of RF Circuits Using Built-in Non-intrusive Sensors. ISVLSI Athanasios Dimakos, Martin Andraud, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu, Salvador Mir
2015	A	`conf`	Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion. ICCAD Ali Ahmadi, Haralampos-G. D. Stratigopoulos, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris
2014	Misc	`conf`	Efficient Monte Carlo-based analog parametric fault modelling. VTS Haralampos-G. D. Stratigopoulos, Stephen Sunter
2014	C	`conf`	Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs. VLSI-SoC Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán
2014	J	`jnl`	Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haralampos-G. D. Stratigopoulos, Stephen Sunter
2014	—	`conf`	Low-cost EVM built-in test of RF transceivers. IDT Ayssar Serhan, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
2014	A*	`conf`	One-Shot Calibration of RF Circuits Based on Non-Intrusive Sensors. DAC Martin Andraud, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu
2014	—	`conf`	Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes. MWSCAS Josep Altet, Eduardo Aldrete-Vidrio, Ferran Reverter, Didac Gómez, José Luis González, Marvin Onabajo, José Silva-Martínez, B. Martineau, X. Perpiñà, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Xavier Aragonès, Xavier Jordà, Miquel Vellvehí, Stefan Dilhaire, Salvador Mir, Diego Mateo
2014	C	`conf`	Solutions for the self-adaptation of communicating systems in operation. IOLTS Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos
2014	—	`conf`	Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST. VLSI-SoC (Selected Papers) Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán
2013	Misc	`conf`	Defect-oriented non-intrusive RF test using on-chip temperature sensors. VTS Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet
2013	A	`conf`	Fault modeling and diagnosis for nanometric analog circuits. ITC Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir
2013	A*	`conf`	Multidimensional analog test metrics estimation using extreme value theory and statistical blockade. DAC Haralampos-G. D. Stratigopoulos, Pierre Faubet, Yoann Courant, Firas Mohamed
2013	—	`conf`	Multivariate statistical techniques for analog parametric test metrics estimation. DTIS Ke Huang, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Salvador Mir, Ahcène Bounceur
2013	Misc	`conf`	Reduced code linearity testing of pipeline adcs in the presence of noise. VTS Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret
2013	J	`jnl`	Reduced-Code Linearity Testing of Pipeline ADCs. IEEE Des. Test Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret
2013	A	`conf`	True non-intrusive sensors for RF built-in test. ITC Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
2012	J	`jnl`	Adaptive Alternate Analog Test. IEEE Des. Test Comput. Haralampos-G. D. Stratigopoulos, Salvador Mir
2012	A	`conf`	Advances in variation-aware modeling, verification, and testing of analog ICs. DATE Dimitri de Jonghe, Elie Maricau, Georges G. E. Gielen, Trent McConaghy, Bratislav Tasic, Haralampos-G. D. Stratigopoulos
2012	J	`jnl`	Diagnosis of Local Spot Defects in Analog Circuits. IEEE Trans. Instrum. Meas. Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir, Camelia Hora, Yizi Xing, Bram Kruseman
2012	B	`conf`	Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs. ETS Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Christophe Forel
2012	A	`conf`	Experiences with non-intrusive sensors for RF built-in test. ITC Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma
2012	J	`jnl`	Guest Editors' Introduction: Digitally Enhanced Wireless Transceivers. IEEE Des. Test Comput. Haralampos-G. D. Stratigopoulos, Alberto Valdes-Garcia
2012	J	`jnl`	Test Metrics Model for Analog Test Development. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haralampos-G. D. Stratigopoulos
2012	A	`conf`	Testing RF circuits with true non-intrusive built-in sensors. DATE Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet
2011	J	`jnl`	Estimation of Analog Parametric Test Metrics Using Copulas. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ahcène Bounceur, Salvador Mir, Haralampos-G. D. Stratigopoulos
2011	J	`jnl`	Guest Editorial. J. Electron. Test. Haralampos-G. D. Stratigopoulos, Krishnendu Chakrabarty
2011	—	`conf`	Implicit test of high-speed analog circuits using non-intrusive sensors. ECCTD Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
2011	—	`conf`	On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study. Asian Test Symposium Alexios Spyronasios, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
2011	A	`conf`	On proving the efficiency of alternative RF tests. ICCAD Nathan Kupp, Haralampos-G. D. Stratigopoulos, Petros Drineas, Yiorgos Makris
2011	J	`jnl`	RF Front-End Test Using Built-in Sensors. IEEE Des. Test Comput. Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma
2010	C	`conf`	An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits. IOLTS Dzmitry Maliuk, Haralampos-G. D. Stratigopoulos, Yiorgos Makris
2010	A	`conf`	Analog neural network design for RF built-in self-test. ITC Dzmitry Maliuk, Haralampos-G. D. Stratigopoulos, He Huang, Yiorgos Makris
2010	A	`conf`	Analog test metrics estimates with PPM accuracy. ICCAD Haralampos-G. D. Stratigopoulos, Salvador Mir
2010	—	`conf`	Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation. Asian Test Symposium Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir
2010	B	`conf`	Defect filter for alternate RF test. ETS Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev
2010	Misc	`conf`	Density estimation for analog/RF test problem solving. VTS Salvador Mir, Haralampos-G. D. Stratigopoulos, Ahcène Bounceur
2010	A	`conf`	Fault diagnosis of analog circuits based on machine learning. DATE Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir
2010	J	`jnl`	RF Specification Test Compaction Using Learning Machines. IEEE Trans. Very Large Scale Integr. Syst. Haralampos-G. D. Stratigopoulos, Petros Drineas, Mustapha Slamani, Yiorgos Makris
2010	B	`conf`	Sensors for built-in alternate RF test. ETS Louay Abdallah, Haralampos-G. D. Stratigopoulos, Christophe Kelma, Salvador Mir
2010	Misc	`conf`	Special session 12A: Panel adaptive analog test: Feasibility and opportunities ahead. VTS Haralampos-G. D. Stratigopoulos
2010	Misc	`conf`	Special session 4C: Thesis research poster session. VTS Haralampos-G. D. Stratigopoulos
2010	Misc	`conf`	Special session 8A: TTTC 2010 E. J. McCluskey Best Doctoral Thesis Award. VTS Haralampos-G. D. Stratigopoulos
2009	B	`conf`	Defect Filter for Alternate RF Test. ETS Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev
2009	A	`conf`	Enrichment of limited training sets in machine-learning-based analog/RF test. DATE Haralampos-G. D. Stratigopoulos, Salvador Mir, Yiorgos Makris
2009	J	`jnl`	Evaluation of Analog/RF Test Measurements at the Design Stage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haralampos-G. D. Stratigopoulos, Salvador Mir, Ahcène Bounceur
2009	C	`conf`	Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study. ICCD Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir
2009	Misc	`conf`	Special Session 7C: TTTC 2009 Best Doctoral Thesis Contest. VTS Yiorgos Makris, Haralampos-G. D. Stratigopoulos
2008	A	`conf`	A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation. DATE Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir
2008	Misc	`conf`	A Statistical Approach to Characterizing and Testing Functionalized Nanowires. VTS James Dardig, Haralampos-G. D. Stratigopoulos, Eric Stern, Mark A. Reed, Yiorgos Makris
2008	J	`jnl`	Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haralampos-G. D. Stratigopoulos, Yiorgos Makris
2007	Misc	`conf`	Non-RF to RF Test Correlation Using Learning Machines: A Case Study. VTS Haralampos-G. D. Stratigopoulos, Petros Drineas, Mustapha Slamani, Yiorgos Makris
2006	J	`jnl`	An adaptive checker for the fully differential analog code. IEEE J. Solid State Circuits Haralampos-G. D. Stratigopoulos, Yiorgos Makris
2006	Misc	`conf`	Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing. VTS Haralampos-G. D. Stratigopoulos, Yiorgos Makris
2006	J	`jnl`	Concurrent detection of erroneous responses in linear analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haralampos-G. D. Stratigopoulos, Yiorgos Makris
2005	Misc	`conf`	Constructive Derivation of Analog Specification Test Criteria. VTS Haralampos-G. D. Stratigopoulos, Yiorgos Makris
2005	—	`conf`	Generating decision regions in analog measurement spaces. ACM Great Lakes Symposium on VLSI Haralampos-G. D. Stratigopoulos, Yiorgos Makris
2005	J	`jnl`	Nonlinear decision boundaries for testing analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haralampos-G. D. Stratigopoulos, Yiorgos Makris
2004	J	`jnl`	An Analog Checker with Input-Relative Tolerance for Duplicate Signals. J. Electron. Test. Haralampos-G. D. Stratigopoulos, Yiorgos Makris
2003	C	`conf`	An Analog Checker With Input-Relative Tolerance for Duplicate Signals. IOLTS Haralampos-G. D. Stratigopoulos, Yiorgos Makris
2003	Misc	`conf`	An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits. VTS Haralampos-G. D. Stratigopoulos, Yiorgos Makris
2003	A	`conf`	Concurrent Error Detection in Linear Analog Circuits Using State Estimation. ITC Haralampos-G. D. Stratigopoulos, Yiorgos Makris