Haoran Li - RankMe

20 papers A* 1A 3C 1Journal 10Unranked 5

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning. IEEE Trans. Very Large Scale Integr. Syst. Haoran Li, Zhongyuan Tian, Jiang Xu, Rafael K. V. Maeda, Zhehui Wang, Zhifei Wang
2020	J	`jnl`	Multidevice Collaborative Power Management Through Decentralized Knowledge Sharing. IEEE Trans. Very Large Scale Integr. Syst. Zhongyuan Tian, Jiang Xu, Haoran Li, Rafael Kioji Vivas Maeda
2019	J	`jnl`	Collaborative Power Management Through Knowledge Sharing Among Multiple Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhongyuan Tian, Zhe Wang, Jiang Xu, Haoran Li, Peng Yang, Rafael Kioji Vivas Maeda
2018	A	`conf`	Co-manage power delivery and consumption for manycore systems using reinforcement learning. ICCAD Haoran Li, Zhongyuan Tian, Rafael K. V. Maeda, Xuanqi Chen, Jun Feng, Jiang Xu
2018	C	`conf`	Decentralized Collaborative Power Management through Multi-Device Knowledge Sharing. ICCD Zhongyuan Tian, Haoran Li, Rafael Kioji Vivas Maeda, Jun Feng, Jiang Xu
2018	—	`conf`	Merge-Based Parallel Sparse Matrix-Sparse Vector Multiplication with a Vector Architecture. HPCC/SmartCity/DSS Haoran Li, Harumichi Yokoyama, Takuya Araki
2018	—	`conf`	Multi-device collaborative management through knowledge sharing. ASP-DAC Zhongyuan Tian, Zhe Wang, Haoran Li, Peng Yang, Rafael Kioji Vivas Maeda, Jiang Xu
2018	J	`jnl`	Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haoran Li, Jiang Xu, Zhe Wang, Rafael K. V. Maeda, Peng Yang, Zhongyuan Tian
2017	A	`conf`	Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators. DATE Haoran Li, Jiang Xu, Zhe Wang, Peng Yang, Rafael K. V. Maeda, Zhongyuan Tian
2017	J	`jnl`	Energy-Efficient Power Delivery System Paradigms for Many-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haoran Li, Xuan Wang, Jiang Xu, Zhe Wang, Rafael K. V. Maeda, Zhehui Wang, Peng Yang, Luan H. K. Duong, Zhifei Wang
2017	A*	`conf`	MOCA: an Inter/Intra-Chip Optical Network for Memory. DAC Zhehui Wang, Zhengbin Pang, Peng Yang, Jiang Xu, Xuanqi Chen, Rafael K. V. Maeda, Zhifei Wang, Luan H. K. Duong, Haoran Li, Zhe Wang
2017	—	`conf`	Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system. ASP-DAC Zhe Wang, Zhongyuan Tian, Jiang Xu, Rafael K. V. Maeda, Haoran Li, Peng Yang, Zhehui Wang, Luan H. K. Duong, Zhifei Wang, Xuanqi Chen
2016	J	`jnl`	A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. Zhehui Wang, Jiang Xu, Peng Yang, Luan Huu Kinh Duong, Zhifei Wang, Xuan Wang, Zhe Wang, Haoran Li, Rafael Kioji Vivas Maeda
2016	J	`jnl`	Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign. ACM J. Emerg. Technol. Comput. Syst. Xuan Wang, Jiang Xu, Zhe Wang, Haoran Li, Peng Yang, Luan H. K. Duong, Rafael K. V. Maeda, Zhifei Wang
2016	J	`jnl`	An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC. IEEE Trans. Very Large Scale Integr. Syst. Zhe Wang, Xuan Wang, Jiang Xu, Haoran Li, Rafael K. V. Maeda, Zhehui Wang, Peng Yang, Luan H. K. Duong, Zhifei Wang
2016	J	`jnl`	Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks. IEEE Trans. Very Large Scale Integr. Syst. Luan H. K. Duong, Zhehui Wang, Mahdi Nikdast, Jiang Xu, Peng Yang, Zhifei Wang, Zhe Wang, Rafael K. V. Maeda, Haoran Li, Xuan Wang, Sébastien Le Beux, Yvain Thonnart
2016	J	`jnl`	Improve Chip Pin Performance Using Optical Interconnects. IEEE Trans. Very Large Scale Integr. Syst. Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan Huu Kinh Duong, Zhifei Wang, Rafael Kioji Vivas Maeda, Haoran Li
2016	—	`conf`	JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models. AISTECS@HiPEAC Rafael K. V. Maeda, Peng Yang, Xiaowen Wu, Zhe Wang, Jiang Xu, Zhehui Wang, Haoran Li, Luan H. K. Duong, Zhifei Wang
2015	A	`conf`	Adaptively tolerate power-gating-induced power/ground noise under process variations. DATE Zhe Wang, Xuan Wang, Jiang Xu, Xiaowen Wu, Zhehui Wang, Peng Yang, Luan H. K. Duong, Haoran Li, Rafael Kioji Vivas Maeda, Zhifei Wang
2015	—	`conf`	Alleviate chip I/O pin constraints for multicore processors through optical interconnects. ASP-DAC Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan H. K. Duong, Zhifei Wang, Haoran Li, Rafael Kioji Vivas Maeda, Xiaowen Wu, Yaoyao Ye, Qinfen Hao