Haolin Han

19 papers Journal 14Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 0.0006-mm
IEEE J. Solid State Circuits
Zhicheng Dong, Xiaoteng Zhao, Zekai Yang, Xianting Su, Haolin Han, Feng Bu, Depeng Sun, Shubin Liu, Zhangming Zhu
2026 J jnl
A 53 dB ripple reduction ratio, 0.68 μ V r m s noise bio-signal analog-front-end with a successive approximation ripple reduction loop.
Microelectron. J.
Shuhang Li, Haolin Han, Wenfei Cao, Shubin Liu
2026 J jnl
Offset-Immune Split-LSB Weight Calibration for Capacitor Mismatch and Gain Nonlinearity in Pipelined SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs
Le Chen, Jinwei Zhang, Shubin Liu, Haolin Han
2025 — conf
24.2 A 14b 1GS/s Single-Channel Pipelined ADC with A Parallel-Operation SAR Sub-Quantizer and A Dynamic-Deadzone Ring Amplifier.
ISSCC
Yue Cao, Yi Shen, Shubin Liu, Haolin Han, Hongzhi Liang, Li Dang, Dengquan Li, Ruixue Ding, Zhangming Zhu
2025 J jnl
A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage.
IEEE J. Solid State Circuits
Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu
2025 — conf
A 32GS/s 8b 16× Time-Interleaved Hybrid ADC with Self-Detection Offset Calibration, DLL-Based TLSB PVT Variation Calibration and VTC Gain Self-Tracking.
CICC
Hongzhi Liang, Jun Chang, Yixiao Luo, Zeyu Peng, Weimin Zhou, Li Dang, Yue Cao, Haolin Han, Yi Shen, Shubin Liu, Ruixue Ding, Zhangming Zhu
2025 J jnl
A linearized PVT-robust FVF input buffer with triode transconductance feedback achieving SFDR > 90 dB at 500-MHz input.
Microelectron. J.
Junye Su, Shubin Liu, Haolin Han
2025 J jnl
A reference-free and derivative-insensitive all-digital calibration technique for timing-skew in TI-ADCs.
Sci. China Inf. Sci.
Li Dang, Shubin Liu, Ruixue Ding, Chengyuan Liu, Hongzhi Liang, Haolin Han, Yue Cao, Zhangming Zhu
2025 J jnl
Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC.
IEEE Trans. Very Large Scale Integr. Syst.
Le Chen, Yue Cao, Lin Ling, Shubin Liu, Haolin Han
2025 J jnl
Rapid digital background calibration of bit weights in pipelined SAR ADC based on multi-PN injection.
Microelectron. J.
Le Chen, Yi Shen, Ruixue Ding, Shubin Liu, Haolin Han
2024 — conf
A 0.0006-mm
A-SSCC
Zhicheng Dong, Xiaoteng Zhao, Zekai Yang, Xianting Su, Haolin Han, Feng Bu, Rong Zhou, Depeng Sun, Yong Chen, Shubin Liu, Ruixue Ding, Zhangming Zhu
2024 J jnl
A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry.
Microelectron. J.
Haolin Han, Ruili Ren, Yi Shen, Ruixue Ding, Shubin Liu, Hongzhi Liang
2024 J jnl
A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique.
Microelectron. J.
Haolin Han, Jinwei Zhang, Ruili Ren, Yi Shen, Shubin Liu, Ruixue Ding
2024 J jnl
A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Haolin Han, Shubin Liu, Hongzhi Liang, Yi Shen, Jianyu Guo, Ruili Ren, Zhangming Zhu
2024 J jnl
A wide load-range OTA using a digitally assisted compensating technique.
Sci. China Inf. Sci.
Haolin Han, Shubin Liu, Yi Shen, Hongzhi Liang, Yue Cao, Longjie Zhong, Zhangming Zhu
2023 — conf
A 0.012mm
CICC
Zhicheng Dong, Shubin Liu, Xiaoteng Zhao, Baotian Hao, Hongzhi Liang, Haolin Han, Menghao Wang, Weijie Han, Zhangming Zhu
2023 — conf
A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage.
CICC
Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu
2020 J jnl
A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shubin Liu, Haolin Han, Yi Shen, Zhangming Zhu
2019 J jnl
Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC.
J. Circuits Syst. Comput.
Shubin Liu, Haolin Han, Ruixue Ding