Hao Zhou - RankMe

40 papers A* 1A 5B 4Misc 3Journal 9Unranked 18

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Accelerator for LLM-Enhanced GNN with Product Quantization and Unified Indexing. ASP-DAC Jiaming Xu, Jinhao Li, Jun Liu, Hao Zhou, Guohao Dai
2025	A	`conf`	AiSpGEMM: Accelerating Imbalanced SpGEMM on FPGAs with Flexible Interconnect and Intra-row Parallel Merging. DATE Enhao Tang, Shun Li, Hao Zhou, Guohao Dai, Jun Lin, Kun Wang
2025	—	`conf`	D-GCN: A Dynamic Pruning Accelerator for Deep Graph Convolutional Networks with Hybrid Dataflow. ACM Great Lakes Symposium on VLSI Shun Li, Hao Zhou, Enhao Tang, Yang Liu, Shidi Tang, Ming Ling
2025	—	`conf`	Deploying Diffusion Models with Scheduling Space Search and Memory Overflow Prevention Based on Graph Optimization. ASP-DAC Hao Zhou, Yang Liu, Hongji Wang, Enhao Tang, Shun Li, Yifan Zhang, Guohao Dai, Yongpan Liu, Kun Wang
2025	A	`conf`	FlightVGM: Efficient Video Generation Model Inference with Online Sparsification and Hybrid Precision on FPGAs. FPGA Jun Liu, Shulin Zeng, Li Ding, Widyadewi Soedarmadji, Hao Zhou, Zehao Wang, Jinhao Li, Jintao Li, Yadong Dai, Kairui Wen, Shan He, Yaqi Sun, Yu Wang, Guohao Dai
2024	J	`jnl`	An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis. ACM Trans. Design Autom. Electr. Syst. Yu Qian, Xuegong Zhou, Hao Zhou, Lingli Wang
2024	A*	`conf`	CSTrans-OPU: An FPGA-based Overlay Processor with Full Compilation for Transformer Networks via Sparsity Exploration. DAC Yueyin Bai, Keqing Zhao, Yang Liu, Hongji Wang, Hao Zhou, Xiaoxing Wu, Jun Yu, Kun Wang
2024	J	`jnl`	Graph-OPU: A Highly Flexible FPGA-Based Overlay Processor for Graph Neural Networks. ACM Trans. Reconfigurable Technol. Syst. Enhao Tang, Shun Li, Ruiqi Chen, Hao Zhou, Yuhanxiao Ma, Haoyang Zhang, Jun Yu, Kun Wang
2024	J	`jnl`	Large Language Model Inference Acceleration: A Comprehensive Hardware Perspective. CoRR Jinhao Li, Jiaming Xu, Shan Huang, Yonghua Chen, Wen Li, Jun Liu, Yaoxiu Lian, Jiayi Pan, Li Ding, Hao Zhou, Yu Wang, Guohao Dai
2024	Misc	`conf`	SDAcc: A Stable Diffusion Accelerator on FPGA via Software-Hardware Co-Design. FCCM Hao Zhou, Yang Liu, Hongji Wang, Enhao Tang, Shun Li, Yifan Zhang, Kun Wang
2023	—	`conf`	AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian Optimization. ICFPT Zhen Li, Hao Zhou, Lingli Wang, Xuegong Zhou
2023	J	`jnl`	An Optimized GIB Routing Architecture with Bent Wires for FPGA. ACM Trans. Reconfigurable Technol. Syst. Kaichuang Shi, Xuegong Zhou, Hao Zhou, Lingli Wang
2023	—	`conf`	Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes. ASICON Jide Zhang, Kaixiang Zhu, Kaichuang Shi, Lingli Wang, Hao Zhou
2023	—	`conf`	Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs. ICFPT Kaichuang Shi, Hao Zhou, Lingli Wang
2023	A	`conf`	FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks. ICCAD Yueyin Bai, Hao Zhou, Keqing Zhao, Hongji Wang, Jianli Chen, Jun Yu, Kun Wang
2023	B	`conf`	LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks. FPL Yueyin Bai, Hao Zhou, Keqing Zhao, Manting Zhang, Jianli Chen, Jun Yu, Kun Wang
2023	Misc	`conf`	Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks. FCCM Yueyin Bai, Hao Zhou, Keqing Zhao, Jianli Chen, Jun Yu, Kun Wang
2023	—	`conf`	VIB: A Versatile Interconnection Block for FPGA Routing Architecture. ICFPT Kaichuang Shi, Hao Zhou, Lingli Wang
2023	—	`conf`	g-BERT: Enabling Green BERT Deployment on FPGA via Hardware-Aware Hybrid Pruning. ICC Yueyin Bai, Hao Zhou, Ruiqi Chen, Kuangjie Zou, Jialin Cao, Haoyang Zhang, Jianli Chen, Jun Yu, Kun Wang
2022	—	`conf`	Efficient Reinforcement Learning Framework for Automated Logic Synthesis Exploration. FPT Yu Qian, Xuegong Zhou, Hao Zhou, Lingli Wang
2022	B	`conf`	GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization. FPL Su Zheng, Jiadong Qian, Hao Zhou, Lingli Wang
2021	—	`conf`	A Hexagon-Based Honeycomb Routing Architecture for FPGA. FPT Kaichuang Shi, Hao Zhou, Lingli Wang
2021	J	`jnl`	A novel DC-DC converter and LDO cascaded circuit with improved dynamic response and loop stability. IEICE Electron. Express Hao Zhou, Hao Min, Ping Luo
2021	—	`conf`	APIR-DSP: An approximate PIR-DSP architecture for error-tolerant applications. FPT Yuan Dai, Simin Liu, Yao Lu, Hao Zhou, Seyedramin Rasoulinezhad, Philip H. W. Leong, Lingli Wang
2021	—	`conf`	General routing architecture modelling and exploration for modern FPGAs. FPT Jiadong Qian, Yuhang Shen, Kaichuang Shi, Hao Zhou, Lingli Wang
2021	B	`conf`	Two-level MUX Design and Exploration in FPGA Routing Architecture. FPL Yuhang Shen, Jiadong Qian, Kaichuang Shi, Lingli Wang, Hao Zhou
2020	—	`conf`	GIB: A Novel Unidirectional Interconnection Architecture for FPGA. FPT Kaichuang Shi, Hao Zhou, Xuegong Zhou, Lingli Wang
2020	A	`conf`	LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. FPGA Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
2020	J	`jnl`	LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. CoRR Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
2020	J	`jnl`	MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. CoRR Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
2019	B	`conf`	Bent Routing Pattern for FPGA. FPL Xibo Sun, Hao Zhou, Lingli Wang
2019	—	`conf`	MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. FPT Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
2019	Misc	`conf`	PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks. FCCM Seyedramin Rasoulinezhad, Hao Zhou, Lingli Wang, Philip H. W. Leong
2018	J	`jnl`	Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hengliang Zhu, Feng Hu, Hao Zhou, David Z. Pan, Dian Zhou, Xuan Zeng
2018	J	`jnl`	Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. IEEE Trans. Very Large Scale Integr. Syst. Hao Zhou, Hengliang Zhu, Tao Cui, David Z. Pan, Dian Zhou, Xuan Zeng
2017	—	`conf`	A fast HDL model for full-custom FPGA verification. ASICON Kaixuan Zhang, Zhihua Feng, Hao Zhou
2015	—	`conf`	An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units. ASICON Weizhen Wang, Hao Zhou, Fan Ye, Junyan Ren
2013	A	`conf`	FPGA bitstream compression and decompression using LZ and golomb coding (abstract only). FPGA Jinsong Mao, Hao Zhou, Haijiang Ye, Jinmei Lai
2013	—	`conf`	Power efficient SAR ADC with optimized settling technique. MWSCAS Weiru Gu, Hao Zhou, Tao Lin, Zhenyu Wang, Fan Ye, Junyan Ren
2011	—	`conf`	FPGA interconnect timing library based on the statistical method. ASICON Xiangzhi Meng, Liguang Chen, Hao Zhou, Jian Wang, Meng Yang, Jinmei Lai