Hao Zheng - RankMe

36 papers A* 13A 6B 1C 3Misc 1Journal 9Unranked 3

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	Scaling Graph Neural Network Training via Geometric Optimization. HPCA Fangzhou Ye, Lingxiang Yin, Hao Zheng
2025	C	`conf`	Attr-RAG: Attribution-Guided Retrieval-Augmented Generation for Scientific Experiment Design. ICMLA Fazle Rahat, M. Shifat Hossain, Arvind Ramanathan, Sumit Kumar Jha, Hao Zheng, Rickard Ewetz
2025	A*	`conf`	DiTile-DGNN: An Efficient Accelerator for Distributed Dynamic Graph Neural Network Inference. ISCA Jiaqi Yang, Hao Zheng, Ahmed Louri
2025	A*	`conf`	I-DGNN: A Graph Dissimilarity-based Framework for Designing Scalable and Efficient DGNN Accelerators. HPCA Jiaqi Yang, Hao Zheng, Ahmed Louri
2025	C	`conf`	Multitask Contrastive Learning using Task-Wise Training and Partitioned Embedding Space. ICMLA M. Shifat Hossain, Sumit Kumar Jha, Hao Zheng, Rickard Ewetz
2025	A*	`conf`	Rethinking Tiling and Dataflow for SpMM Acceleration: A Graph Transformation Framework. MICRO Amir Ghazizadeh Ahsaei, Lingxiang Yin, Shilin Tian, Fangzhou Ye, Fan Yao, Hao Zheng
2024	A	`conf`	Aurora: A Versatile and Flexible Accelerator for Graph Neural Networks. IPDPS Jiaqi Yang, Hao Zheng, Ahmed Louri
2024	A	`conf`	CircuitSeer: RTL Post-PnR Delay Prediction via Coupling Functional and Structural Representation. ICCAD Sanjay Gandham, Joe Walston, Sourav Samanta, Lingxiang Yin, Hao Zheng, Mingjie Lin, Stelios Diamantidis
2024	—	`conf`	CryptoTrain: Fast Secure Training on Encrypted Dataset. LAMPS@CCS Jiaqi Xue, Yancheng Zhang, Yanshan Wang, Xueqiang Wang, Hao Zheng, Qian Lou
2024	A*	`conf`	EGMA: Enhancing Data Reuse and Workload Balancing in Message Passing GNN Acceleration via Gram Matrix Optimization. DAC Fangzhou Ye, Lingxiang Yin, Amir Ghazizadeh Ahsaei, Hao Zheng
2024	A*	`conf`	MetaLeak: Uncovering Side Channels in Secure Processor Architectures Exploiting Metadata. ISCA Md Hafizul Islam Chowdhuryy, Hao Zheng, Fan Yao
2024	J	`jnl`	Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration. IEEE Trans. Sustain. Comput. Ke Wang, Hao Zheng, Jiajun Li, Ahmed Louri
2024	A*	`conf`	SCALE: A Structure-Centric Accelerator for Message Passing Graph Neural Networks. MICRO Lingxiang Yin, Sanjay Gandham, Mingjie Lin, Hao Zheng
2024	B	`conf`	Towards Area-Efficient Path-Based In-Memory Computing using Graph Isomorphisms. ASPDAC Sven Thijssen, Muhammad Rashedul Haq Rashed, Hao Zheng, Sumit Kumar Jha, Rickard Ewetz
2024	A*	`conf`	VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design. DAC Shilin Tian, Chase Szafranski, Ce Zheng, Fan Yao, Ahmed Louri, Chen Chen, Hao Zheng
2024	J	`jnl`	Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration. IEEE Trans. Parallel Distributed Syst. Jiaqi Yang, Hao Zheng, Ahmed Louri
2023	A	`conf`	ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects. ICCAD Lingxiang Yin, Amir Ghazizadeh, Ahmed Louri, Hao Zheng
2023	—	`conf`	Exploring Architecture, Dataflow, and Sparsity for GCN Accelerators: A Holistic Framework. ACM Great Lakes Symposium on VLSI Lingxiang Yin, Jun Wang, Hao Zheng
2023	A*	`conf`	FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations. ISCA Jiajun Li, Yuxuan Zhang, Hao Zheng, Ke Wang
2023	J	`jnl`	GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators. J. Comput. Sci. Technol. Jiajun Li, Ke Wang, Hao Zheng, Ahmed Louri
2023	Misc	`conf`	OCMGen: Extended Design Space Exploration with Efficient FPGA Memory Inference. FCCM Sanjay Gandham, Lingxiang Yin, Hao Zheng, Mingjie Lin
2023	A	`conf`	Path-Based Processing using In-Memory Systolic Arrays for Accelerating Data-Intensive Applications. ICCAD Muhammad Rashedul Haq Rashed, Sven Thijssen, Sumit Kumar Jha, Hao Zheng, Rickard Ewetz
2023	C	`conf`	Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration. ICCD Lingxiang Yin, Amir Ghazizadeh, Shilin Tian, Ahmed Louri, Hao Zheng
2023	A	`conf`	SAGA: Sparsity-Agnostic Graph Convolutional Network Acceleration with Near-Optimal Workload Balance. ICCAD Sanjay Gandham, Lingxiang Yin, Hao Zheng, Mingjie Lin
2023	A*	`conf`	Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications. DAC Jiaqi Yang, Hao Zheng, Ahmed Louri
2022	A	`conf`	AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems. DATE Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, Ahmed Louri
2022	—	`conf`	Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation. ACM Great Lakes Symposium on VLSI Jiaqi Yang, Hao Zheng, Ahmed Louri
2022	J	`jnl`	Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip Design. IEEE Trans. Emerg. Top. Comput. Hao Zheng, Ahmed Louri
2022	J	`jnl`	Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. Yuan Li, Ke Wang, Hao Zheng, Ahmed Louri, Avinash Karanth
2022	J	`jnl`	SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing. IEEE Trans. Parallel Distributed Syst. Jiajun Li, Hao Zheng, Ke Wang, Ahmed Louri
2022	J	`jnl`	SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design. IEEE Trans. Sustain. Comput. Ke Wang, Hao Zheng, Yuan Li, Ahmed Louri
2021	A*	`conf`	Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures. HPCA Hao Zheng, Ke Wang, Ahmed Louri
2020	A*	`conf`	A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures. DAC Hao Zheng, Ke Wang, Ahmed Louri
2020	J	`jnl`	TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture. IEEE Micro Ke Wang, Hao Zheng, Ahmed Louri
2019	A*	`conf`	An Energy-Efficient Network-on-Chip Design using Reinforcement Learning. DAC Hao Zheng, Ahmed Louri
2018	J	`jnl`	EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs. IEEE Comput. Archit. Lett. Hao Zheng, Ahmed Louri