Hao Zheng - RankMe

66 papers A* 3C 5Misc 1Journal 30Unranked 26

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	AutoFlows: Inferring Message Flows from System Communication Traces. ISQED Bardia Nadimi, Hao Zheng
2025	A*	`conf`	PyraNet: A Multi-Layered Hierarchical Dataset for Verilog. DAC Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
2025	J	`jnl`	TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation. CoRR Bardia Nadimi, Khashayar Filom, Deming Chen, Hao Zheng
2025	J	`jnl`	VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric. CoRR Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
2024	J	`jnl`	A Multi-Expert Large Language Model Architecture for Verilog Code Generation. CoRR Bardia Nadimi, Hao Zheng
2024	J	`jnl`	AutoModel: Automatic Synthesis of Models From Communication Traces of SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Md Rubel Ahmed, Bardia Nadimi, Hao Zheng
2024	J	`jnl`	Inferring Message Flows From System Communication Traces. CoRR Bardia Nadimi, Hao Zheng
2024	J	`jnl`	PyraNet: A Large Scale Hierarchical Verilog Dataset. CoRR Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
2024	—	`conf`	Rare-Event Guided Analysis of Infinite-State Chemical Reaction Networks. QEST+FORMATS Mohammad Ahmadi, Lukas Buecherl, Chris J. Myers, Zhen Zhang, Chris Winstead, Hao Zheng
2023	J	`jnl`	AutoModel: Automatic Synthesis of Models from Communication Traces of SoC Designs. CoRR Md Rubel Ahmed, Bardia Nadimi, Hao Zheng
2023	—	`conf`	STAMINA in C++: Modernizing an Infinite-State Probabilistic Model Checker. QEST Joshua Jeppson, Matthias Volk, Bryant Israelsen, Riley Roberts, Andrew Williams, Lukas Buecherl, Chris J. Myers, Hao Zheng, Chris Winstead, Zhen Zhang
2023	—	`conf`	System-on-Chip Message Flow Mining with Masked-Language Models. MWSCAS Md Rubel Ahmed, Bardia Nadimi, Hao Zheng
2022	J	`jnl`	Counterexample Generation for Infinite-State Chemical Reaction Networks. CoRR Mohammad Ahmadi, Zhen Zhang, Chris J. Myers, Chris Winstead, Hao Zheng
2022	J	`jnl`	Deep Bidirectional Transformers for SoC Flow Specification Mining. CoRR Md Rubel Ahmed, Hao Zheng
2022	J	`jnl`	Mining Patterns From Concurrent Execution Traces. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2022	J	`jnl`	Mining SoC Message Flows with Attention Model. CoRR Md Rubel Ahmed, Bardia Nadimi, Hao Zheng
2021	—	`conf`	A Comparative Study of Specification Mining Methods for SoC Communication Traces. ISVLSI Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2021	—	`conf`	Mining Message Flows from System-on-Chip Execution Traces. ISQED Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2021	C	`conf`	Model Synthesis for Communication Traces of System Designs. ICCD Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2021	J	`jnl`	Model Synthesis for Communication Traces of System-on-Chip Designs. CoRR Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2021	J	`jnl`	Tools and Algorithms for SoC Communication Traces. CoRR Md Rubel Ahmed, Hao Zheng
2020	—	`conf`	A Distributed Framework for Real Time Object Detection at Low Frame Rates with IoT Edge Nodes. iSES Lakshmi Kavya Kalyanam, Vishalini Laguduva Ramnath, Srinivas Katkoori, Hao Zheng
2020	J	`jnl`	A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug. CoRR Yuting Cao, Hao Zheng, Sandip Ray, Jin Yang
2020	J	`jnl`	Local State Space Analysis to Assist Partial Order Reduction. CoRR Hao Zheng, Yingying Zhang, Chris J. Myers
2020	J	`jnl`	Mining Message Flows from System-on-Chip Execution Traces. CoRR Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2020	—	`conf`	Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs. ISQED Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng
2020	J	`jnl`	Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs. CoRR Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng
2020	—	`conf`	Stream-Monitoring Automata. ICSCA Hernan M. Palombo, Egor Dolzhenko, Jay Ligatti, Hao Zheng
2020	J	`jnl`	Using Decision Diagrams to Compactly Represent the State Space for Explicit Model Checking. CoRR Hao Zheng, Andrew Price, Chris J. Myers
2019	—	`conf`	A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug. ISQED Yuting Cao, Hao Zheng, Sandip Ray
2019	J	`jnl`	A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug. CoRR Yuting Cao, Hao Zheng, Sandip Ray
2019	J	`jnl`	Approximation Techniques for Stochastic Analysis of Biological Systems. CoRR Thakur Neupane, Zhen Zhang, Curtis Madsen, Hao Zheng, Chris J. Myers
2019	—	`ch.`	Approximation Techniques for Stochastic Analysis of Biological Systems. Automated Reasoning for Systems Biology and Medicine Thakur Neupane, Zhen Zhang, Curtis Madsen, Hao Zheng, Chris J. Myers
2019	—	`conf`	STAMINA: STochastic Approximate Model-Checker for INfinite-State Analysis. CAV (1) Thakur Neupane, Chris J. Myers, Curtis Madsen, Hao Zheng, Zhen Zhang
2019	J	`jnl`	STAMINA: STochastic Approximate Model-checker for INfinite-state Analysis. CoRR Thakur Neupane, Chris J. Myers, Curtis Madsen, Hao Zheng, Zhen Zhang
2018	—	`conf`	Enhancing Observability for Post-Silicon Debug with On-chip Communication Monitors. ISVLSI Yuting Cao, Hernan M. Palombo, Sandip Ray, Hao Zheng
2017	C	`conf`	A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug. ICCD Yuting Cao, Hao Zheng, Hernan M. Palombo, Sandip Ray, Jin Yang
2017	A*	`conf`	POSTER: Towards Precise and Automated Verification of Security Protocols in Coq. CCS Hernan M. Palombo, Hao Zheng, Jay Ligatti
2016	J	`jnl`	An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis. Sci. Comput. Program. Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers
2016	—	`conf`	Protocol-guided analysis of post-silicon traces under limited observability. ISQED Hao Zheng, Yuting Cao, Sandip Ray, Jin Yang
2015	J	`jnl`	Compositional Model Checking of Concurrent Systems. IEEE Trans. Computers Hao Zheng, Zhen Zhang, Chris J. Myers, Emmanuel Rodriguez, Yingying Zhang
2014	C	`conf`	Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip. FMICS Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers
2014	J	`jnl`	Local State Space Analysis Leads to Better Partial Order Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao Zheng, Yingying Zhang
2014	—	`conf`	Local state space construction for compositional verification of concurrent systems. SPIN Hao Zheng
2012	—	`conf`	A Compositional Minimization Approach for Large Asynchronous Design Verification. SPIN Hao Zheng, Emmanuel Rodriguez, Yingying Zhang, Chris J. Myers
2012	—	`conf`	An Improvement in Partial Order Reduction Using Behavioral Analysis. ISVLSI Yingying Zhang, Emmanuel Rodriguez, Hao Zheng, Chris J. Myers
2012	—	`conf`	Poster Abstract: Methods and Tools for Verification of Cyber-Physical Systems. ICCPS Chris J. Myers, Jian Wu, Zhen Zhang, Hao Zheng, Yingying Zhang
2012	—	`conf`	Using decision diagrams to compactly represent the state space for explicit model checking. HLDVT Hao Zheng, Andrew Price, Chris J. Myers
2011	—	`conf`	A Behavioral Analysis Approach for Efficient Partial Order Reduction. HASE Yingying Zhang, Emmanuel Rodriguez, Hao Zheng, Chris J. Myers
2010	—	`conf`	Automatic abstraction for verification of cyber-physical systems. ICCPS Robert A. Thacker, Kevin R. Jones, Chris J. Myers, Hao Zheng
2010	J	`jnl`	Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement. IEEE Trans. Computers Hao Zheng, Haiqiong Yao, Tomohiro Yoneda
2010	—	`conf`	State space reductions for scalable verification of asynchronous designs. HLDVT Haiqiong Yao, Hao Zheng, Chris J. Myers
2009	J	`jnl`	Automated Interface Refinement for Compositional Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haiqiong Yao, Hao Zheng
2009	—	`conf`	Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs. ISVLSI Hao Zheng, Haiqiong Yao, Tomohiro Yoneda
2008	J	`jnl`	A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao Zheng, Jared Ahrens, Tian Xia
2007	J	`jnl`	Timing Jitter Characterization for Mixed-Signal Production Test Using the Interpolation Algorithm. IEEE Trans. Ind. Electron. Tian Xia, Hao Zheng
2006	—	`conf`	Data Dependent Jitter Characterization Based on Fourier Analysis. DFT Di Mu, Tian Xia, Hao Zheng
2006	J	`jnl`	Verification of timed circuits with failure-directed abstractions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
2005	—	`conf`	Characterizing the VCO jitter due to the digital simultaneous switching noise. ACM Great Lakes Symposium on VLSI Tian Xia, Peilin Song, Hao Zheng
2005	—	`conf`	Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators. ISVLSI Tian Xia, Hao Zheng, Jing Li, Ahmed Ginawi
2003	J	`jnl`	Modular verification of timed circuits using automatic abstraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao Zheng, Eric Mercer, Chris J. Myers
2003	C	`conf`	Verification of Timed Circuits with Failure Directed Abstractions. ICCD Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
2001	A*	`conf`	Automatic Abstraction for Verification of Timed Circuits and Systems. CAV Hao Zheng, Eric Mercer, Chris J. Myers
2001	—	`conf`	Timed circuits: a new paradigm for high-speed design. ASP-DAC Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng
1999	C	`conf`	Architectural Synthesis of Timed Asynchronous Systems. ICCD Brandon M. Bachman, Hao Zheng, Chris J. Myers
1997	Misc	`conf`	An asynchronous implementation of the maxlist algorithm. ICASSP Chris J. Myers, Hao Zheng