Hao Xu

33 papers Journal 18Unranked 15
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 28-nm 8-28-GHz Eight-Phase Clock Generator Using an Injection-Locked Dual-Feedback Ring Oscillator.
IEEE J. Solid State Circuits
Yechen Tian, Junjie Gu, Weitao He, Shuai Liu, Rui Yin, Xiaoliang Shen, Long Kong, Hao Xu, Na Yan
2026 J jnl
Efficient Time-Skew Calibration for Time-Interleaved ADC via Matrix Binary Decomposition and Increment-Based Adaption.
IEEE Trans. Circuits Syst. II Express Briefs
Fanshu Ye, Yechen Tian, Shuai Liu, Hao Xu, Na Yan
2025 — conf
19.11 A 13GHz Charge-Pump PLL Achieving 15.8fs
ISSCC
Depeng Sun, Feng Bu, Qixian Ye, Shijie Li, Yuan Gao, Bowen Wang, Hao Xu, Na Yan, Shubin Liu, Zhangming Zhu
2025 J jnl
A 0.2-19GHz Zero-IF Reconfigurable Quadrature Transmitter With T-Coil Matching Network.
IEEE Trans. Circuits Syst. II Express Briefs
An Sun, Yaxin Zeng, Haoqi Qin, Hao Xu, Rui Yin, Xiaoliang Shen, Lifeng Bian, Na Yan
2025 J jnl
A 12-bit 2GS/s current-steering DAC with 27 mW power consumption in 28 nm CMOS.
Microelectron. J.
Beiqi Duan, Junyan Bi, Hao Xu, Guoyu Li, Yechen Tian, Na Yan
2025 J jnl
A 2 MHz-BW 80.6 dB-SNDR 95.9 dB-SFDR 2nd-order noise-shaping SAR using open-loop Gm-R amplifier.
Microelectron. J.
Hao Xu, Congyang Sun, Shuai Liu, Guoyu Li, Yechen Tian, Na Yan
2025 J jnl
A 25-31-GHz Compact True Power Detector With >33-dB Dynamic Range and Intrinsic Phase Offset Compensation in 40-nm Bulk CMOS.
IEEE J. Solid State Circuits
Haoqi Qin, Junjie Gu, Hao Xu, Zhiwei Xu, Pengcheng Jia, Na Yan
2025 J jnl
A 5-18-GHz Reconfigurable Quadrature Receiver With Enhanced I-Q Isolation and 100-500-MHz Baseband Bandwidth.
IEEE J. Solid State Circuits
Junyan Bi, Hao Xu, Tenghao Zou, Yaxin Zeng, Yechen Tian, Weitao He, Junjie Gu, Ziyang Jiao, Shubin Liu, Zhangming Zhu, Na Yan
2025 J jnl
An All-Digital Spread-Spectrum Clock Generator With Feedforward Gain Calibration for LPWAN Chirp Transmission System.
IEEE Trans. Circuits Syst. II Express Briefs
Yiyun Mao, Haoyuan Gao, Jin Shao, Xinyi Lin, Peifang Wu, Ping Lu, Hao Xu, Na Yan
2025 J jnl
Design and Analysis of a 26-32-GHz 6-bit Passive Vector Modulation Phase Shifter for CMOS Bidirectional Transceiver.
IEEE Trans. Very Large Scale Integr. Syst.
Yechen Tian, Yutong Zhang, Junjie Gu, Hao Xu, Weitian Liu, Rui Yin, Zongming Duan, Hao Gao, Na Yan
2025 J jnl
Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shuai Liu, Yechen Tian, Congyang Sun, Guoyu Li, Hao Xu, Na Yan
2024 — conf
5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression.
ISSCC
Hao Xu, Junyan Bi, Tenghao Zou, Weitao He, Yaxin Zeng, Junjie Gu, Ziyang Jiao, Shubin Liu, Zhangming Zhu, Na Yan
2024 J jnl
A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yan Liu, Haoyuan Gao, Hao Xu, Ping Lu, Na Yan
2024 — conf
An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS.
CICC
Yizhuo Wang, Hao Xu, Guoyu Li, Shuai Liu, Yan Liu, Rui Yin, Hui Pan, Na Yan
2024 J jnl
Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Xu, Shujiang Ji, Yizhuo Wang, Xinyi Lin, Hao Min, Na Yan
2023 J jnl
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier.
IEEE J. Solid State Circuits
Wenning Jiang, Yan Zhu, Chixiao Chen, Hao Xu, Qi Liu, Ming Liu, Rui Paulo Martins, Chi-Hang Chan
2023 — conf
A 26-30GHz Digitally-Controlled Variable Gain Power Amplifier with Phase Compensation and Third Order Nonlinearity Cancellation Technique.
A-SSCC
Haoqi Qin, Junjie Gu, Hao Xu, Weitian Liu, Kefeng Han, Rui Yin, Zongming Duan, Hao Gao, Na Yan
2023 J jnl
A 6-12 GHz Wideband Low-Noise Amplifier With 0.8-1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tenghao Zou, Hao Xu, Yizhuo Wang, Weitian Liu, Tingting Han, Mi Tian, Weiqiang Zhu, Na Yan
2023 — conf
A High Speed, Low Power and Low Phase Noise Divider for Wideband Application.
ASICON
Xinyi Lin, Hao Xu, Dejian Li, Na Yan
2023 — conf
A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS.
ASICON
Peifang Wu, Yan Liu, Xi Feng, Hao Xu, Na Yan
2023 — conf
An ADPLL Design Model Based on LoRa IoT Application.
ASICON
Yiyun Mao, Haoyuan Gao, Dejian Li, Hao Xu, Na Yan
2023 J jnl
Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL.
IEEE J. Solid State Circuits
Yizhuo Wang, Jiahe Shi, Hao Xu, Shujiang Ji, Yiyun Mao, Tenghao Zou, Jun Tao, Hao Min, Na Yan
2023 — conf
Analysis and Modeling of Non-ideal Effects in SAR ADC.
ASICON
Yaxin Zeng, Hao Xu, Xi Feng, Na Yan
2023 — conf
INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications.
ICTA
Haoyuan Gao, Hao Xu, Xinyi Lin, Yan Liu, Zhidong Tang, Xufeng Kou, Xingyu Zhang, Tetsuya Iizuka, Na Yan
2022 — conf
A 6-18GHz Low-Noise Amplifier Using Noise Canceling Technique in 130-nm CMOS PD-SOI.
ICTA
Jialong Xue, Tenghao Zou, Hao Xu, Tingting Han, Mi Tian, Weiqiang Zhu, Zhijian Li, Na Yan
2021 — conf
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW.
ESSCIRC
Tetsuya Iizuka, Hao Xu, Asad A. Abidi
2021 — conf
An 800MS/s, 6.7b ENOB Bootstrap Switching S/H IC for Wideband Direct RF Sub-Sampling Receiver in 45 nm CMOS.
ASICON
Shuai Liu, Rui Yin, Hao Xu, Xiaoliang Shen, Na Yan
2019 — conf
A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs.
ISSCC
Dihang Yang, Asad A. Abidi, Hooman Darabi, Hao Xu, David Murphy, Hao Wu, Zhaowen Wang
2019 J jnl
Analysis and Design of Regenerative Comparators for Low Offset and Noise.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Xu, Asad A. Abidi
2017 J jnl
Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Xu, Asad A. Abidi
2015 J jnl
A Noise-Cancelling Receiver Resilient to Large Harmonic Blockers.
IEEE J. Solid State Circuits
David Murphy, Hooman Darabi, Hao Xu
2014 — conf
3.6 A noise-cancelling receiver with enhanced resilience to harmonic blockers.
ISSCC
David Murphy, Hooman Darabi, Hao Xu
2014 — conf
Understanding the regenerative comparator circuit.
CICC
Asad A. Abidi, Hao Xu