Hao Cai

144 papers A* 3A 4C 6Misc 2Journal 58Unranked 69
YearRankTypeTitle / Venue / Authors
2026 — conf
30.1 A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-Sliding Schemes.
ISSCC
Xing Wang, Yucheng Du, Tianhui Jiao, Defa Wu, Xi Chen, Miaoyu Tang, Yi Yang, Zhichao Liu, An Guo, Gaoming Fu, Peng Li, Jun Dong, Bo Liu, Xinning Liu, Weiwei Shan, Hao Cai, Guangyu Sun, Lin Tong, Jun Yang, Xin Si
2026 — conf
A 51.6μJ/Token Subspace-Rotation-Based Dual-Quantized Large-language-Model Accelerator with Fused Scale-Activation INT Datapath and Rearranged Bit-Slice LUT Computation.
ISSCC
Bo Liu, Zihan Zou, Xinming Yan, Xilong Kang, Xinyang Chen, Bo Hu, Jiaming Lin, Haoran Du, Jun Yang, Xin Si, Hao Cai
2026 J jnl
A Versatile One-Time-Programmable STT-MRAM for Security-Aware Scenario.
IEEE Trans. Reliab.
Jiongzhe Su, Haoran Du, Mingtao Chen, Keyang Zhang, Yichen Zhu, Quanhai Zhu, Bo Liu, Hao Cai
2026 J jnl
A highly stable high-speed 11T SRAM for energy-efficient operation.
Microelectron. J.
Yefan Xu, Kaili Zhang, Deming Zhang, Yu Gong, Hao Cai, You Wang, Weiqiang Liu
2026 J jnl
Elaborated Dual-Path SOT-MRAM Achieving 500-MHz Read and 100-MHz Write for Energy-Constraint Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhenghan Fang, Hongjin Zhu, Haoran Du, Shuyu Wang, Hao Cai
2025 — conf
14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers.
ISSCC
Xing Wang, Tianhui Jiao, Yi Yang, Shaochen Li, Dongqi Li, An Guo, Yuhui Shi, Yuchen Tang, Jinwu Chen, Zhican Zhang, Zhichao Liu, Bo Liu, Weiwei Shan, Xin Wang, Hao Cai, Wenwu Zhu, Jun Yang, Xin Si
2025 — conf
14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer.
ISSCC
Xi Chen, Shaochen Li, Zhican Zhang, Wentao Zheng, Xiao Tan, Yuchen Tang, Yuhui Shi, Lizheng Ren, Yibo Mai, Feiran Liu, Jinwu Chen, Zhaoyang Zhang, An Guo, Tianzhu Xiong, Bo Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Jun Yang, Xin Si
2025 — conf
14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching.
ISSCC
An Guo, Jingmin Zhang, Xingyu Pu, Yi Yang, Defa Wu, Yuchen Tang, Yuhui Shi, Yinghai Gao, Zhichao Liu, Bo Wang, Tianzhu Xiong, Zhaoyang Zhang, Xi Chen, Jinwu Chen, Feiran Liu, Xing Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Xin Si, Jun Yang
2025 — conf
A 40nm 4Mb High-Reliability STT-MRAM Achieving 18ns Write-Time and 94.9% Wafer-Level-Die-Yield Across -55°C-to-125°C.
CICC
Yaoru Hou, Haoran Du, Jiongzhe Su, Yibo Liu, Zhenghan Fang, Jia-Le Cui, Shuyu Wang, Chenxing Liu-Sun, Xuezhao Wu, Zhihua Xiao, Bo Liu, Xin Si, Jun Yang, Qiming Shao, Hao Cai
2025 — conf
A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs.
CICC
Bo Liu, Xingyu Xu, Yang Zhang, Xilong Kang, Qingwen Wei, Zihan Zou, Jun Yang, Hao Cai, Xin Si
2025 — conf
A Hardware Prototype of an MRAM-based Stochastic Computing System.
ACM Great Lakes Symposium on VLSI
Zhengkun Yu, Tianhan Fei, Hao Cai, Heng Shi, Yumeng Yang, Siting Liu
2025 — conf
AmPEC: Approximate MRAM with Partial Error Correction for Fine-grained Energy-quality Trade-off.
ASP-DAC
Lan-yang Sun, Yaoru Hou, Hao Cai
2025 J jnl
Energy Efficient On-Chip Memory for Next Generation MCU.
IEEE Trans. Circuits Syst. II Express Briefs
Longning Qi, Jinqi Fan, Tongheng Rao, Meiyan Lv, Jingu Ma, Hao Cai
2025 A conf
H3D-LLM: Heterogeneous 3D Chiplet Design for LLM Inference with Dynamic Task Scheduling and Memory-Aware Orchestration.
ICCAD
Hui Kou, Chenjie Xia, Jialin Yang, Liyi Li, Hao Cai, Xin Si, Bo Liu
2025 J jnl
KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM.
IEEE Trans. Circuits Syst. II Express Briefs
Yang Zhang, Xilong Kang, Weixuan Wang, Yizhi Ding, Lizheng Ren, Yiran Zhang, Ruiqi Tan, Zhen Wang, Hao Cai, Bo Liu
2025 A* conf
OutlierCIM: Outlier-Aware Digital CIM-Based LLM Accelerator with Hybrid-Strategy Quantization and Unified FP-INT Computation.
DAC
Zihan Zou, Shikuang Chen, Chen Zhang, Xing Wang, Zhichao Liu, Haoran Du, Xin Si, Hao Cai, Bo Liu
2025 J jnl
PF²A-ViT: Parameter-Free and Feature-Aware Dynamic Token Pruning Accelerator With Complementary Quantization-Encoding for Vision Transformer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zihan Zou, Xinming Yan, Chen Zhang, Shikuang Chen, Guang Yang, Han Yan, Hao Cai, Bo Liu
2025 — conf
Reference-Free Single-Ended Spin-Transfer Torque MRAM with Low-Power Sensing.
NewCAS
Miao Yu, Shuyu Wang, Xiaoyun Tian, Hao Cai
2025 A* conf
S-DMA: Sparse Diffusion Models Acceleration via Spatiality-Aware Prediction and Dimension-Adaptive Dataflow.
MICRO
Zihan Zou, Xinming Yan, Shun Zhang, Peng Zheng, Guang Yang, Hao Cai, Bo Liu
2025 — conf
SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device.
ASP-DAC
Xilong Kang, Qingwen Wei, Ningyuan Li, Xingyu Xu, Hao Cai, Bo Liu
2025 — conf
Serial Magnetoresistance Accumulation Supported Spiking Neural Network in STT-MRAM.
NewCAS
Xiaoyun Tian, Zhongjian Bian, Bo Liu, Xin Si, Hao Cai
2025 — conf
TWDP: A Vision Transformer Accelerator with Token-Weight Dual-Pruning Strategy for Edge Device Deployment.
ASP-DAC
Guang Yang, Xinming Yan, Hui Kou, Zihan Zou, Qingwen Wei, Hao Cai, Bo Liu
2024 — conf
22 nm Ultra-Low Power MCU with 43.5nW/KB Sleep Retention Power for Automotive Grade-1 Applications.
ICTA
Yibo Liu, Wen Wang, Hongjin Zhu, Longning Qi, Bo Liu, Xinning Liu, Jun Yang, Hao Cai
2024 — conf
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.
ISSCC
An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si
2024 — conf
A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs.
A-SSCC
An Guo, Xueshan Dong, Fangyuan Dong, Dongqi Li, Yiran Zhang, Jingmin Zhang, Yuchen Tang, Yuhui Shi, Xiao Tan, Bo Liu, Weiwei Shan, Hao Cai, Jun Yang, Xin Si
2024 J jnl
A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu
2024 — conf
An Index-free Coding Compression Mechanism for Vision Transformers.
ICTA
Han Yan, Zihan Zou, Shikuang Chen, Chen Zhang, Guang Yang, Hao Cai, Bo Liu
2024 — conf
Cache-Like Dual-Port SOT-MRAM with Read-while-Write Access Strategy.
ICTA
Keyang Zhang, Bo Liu, Hao Cai
2024 C conf
Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory.
ISCAS
Rong Zhou, Bo Liu, Xin Si, Hao Cai
2024 A* conf
FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow.
DAC
Bo Liu, Qingwen Wei, Yang Zhang, Xingyu Xu, Zihan Zou, Xinxiang Huang, Xin Si, Hao Cai
2024 J jnl
Intrinsic MRAM Properties Enable Security Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Haoran Du, You Wang, Jun Yang, Hao Cai
2024 J jnl
Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Zeju Li, Qinfan Wang, Zihan Zou, Qiao Shen, Na Xie, Hao Cai, Hao Zhang, Bo Liu
2024 J jnl
Layer-Wise Mixed-Modes CNN Processing Architecture With Double-Stationary Dataflow and Dimension-Reshape Strategy.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bo Liu, Xinxiang Huang, Yang Zhang, Guang Yang, Han Yan, Chen Zhang, Zejv Li, Yuanhao Wang, Hao Cai
2024 C conf
Live Demonstration: A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing.
ISCAS
Chenjie Xia, Xuanhao Zhang, Zihan Zou, Hao Cai, Bo Liu
2024 J jnl
Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin Chen, Yuxin Bai, Hao Cai, Congyi Zhu, Xinjie Zhou, Ying Zhang, Weiqiang Liu
2024 J jnl
On-Chip-Registration Supported ASR Processor Using Two-Step Transfer-Learning TWN.
IEEE Trans. Circuits Syst. II Express Briefs
Bo Liu, Xuanhao Zhang, Hui Kou, Chenjie Xia, Zhen Wang, Hao Cai
2024 Misc conf
Small-Footprint Automatic Speech Recognition System using Two-Stage Transfer Learning based Symmetrized Ternary Weight Network.
ICASSP
Xuanhao Zhang, Hui Kou, Chenjie Xia, Hao Cai, Bo Liu
2024 J jnl
Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference.
IEEE Trans. Emerg. Top. Comput.
Jia-Le Cui, Yanan Guo, Juntong Chen, Bo Liu, Hao Cai
2024 J jnl
Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bo Liu, Na Xie, Qingwen Wei, Guang Yang, Chonghang Xie, Weiqiang Liu, Hao Cai
2024 — conf
Towards Reliability MRAM for Energy-Efficient Spin-orbit Torque Switching.
SBCCI
Zhenghan Fang, Lirida Naviner, Wen Wang, Wei Le, Hao Cai
2024 — conf
Truly Random Number Generation by Using in-Plane Magnetic Tunnel Junction with Weak Anisotropy.
AsianHOST
You Wang, Chaoyue Zhang, Yefan Xu, Yu Gong, Hao Cai, Weiqiang Liu
2024 — conf
Unveiling Security MRAM-OTP Macro using MTJ Hard Breakdown Mechanism.
AsianHOST
Jiongzhe Su, Haoran Du, Quanhai Zhu, Mingtao Chen, Keyang Zhang, Bo Liu, Hao Cai
2024 J jnl
VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Yu Gong, Bo Liu, Hao Cai, Longxing Shi, Weiqiang Liu
2023 — conf
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.
ISSCC
Hao Cai, Zhongjian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan
2023 — conf
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
ISSCC
An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang
2023 — conf
A FinFET Integrated STT-MRAM with Triple Balanced Access Strategy.
ICTA
Xinshu Xie, Jiongzhe Su, Hao Zhang, Hao Cai
2023 J jnl
A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment.
IEEE Trans. Circuits Syst. II Express Briefs
Bo Liu, Anfeng Xue, Ziyu Wang, Na Xie, Xuetao Wang, Zhen Wang, Hao Cai
2023 J jnl
A Survey of MRAM-Centric Computing: From Near Memory to In Memory.
IEEE Trans. Emerg. Top. Comput.
Yueting Li, Tianshuo Bai, Xinyi Xu, Yundong Zhang, Bi Wu, Hao Cai, Biao Pan, Weisheng Zhao
2023 J jnl
AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS.
IEEE J. Solid State Circuits
Weiwei Shan, Junyi Qian, Lixuan Zhu, Jun Yang, Cheng Huang, Hao Cai
2023 — conf
An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis.
ICTA
Qingwen Wei, Yang Zhang, Xingyu Xu, Hao Cai, Bo Liu
2023 J jnl
Computing in-memory with cascaded spintronic devices for AI edge.
Comput. Electr. Eng.
Zhongjian Bian, Bo Liu, Hao Cai
2023 J jnl
Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms.
IEEE Des. Test
Hao Cai, Yaoru Hou, Mengdi Zhang, Bo Liu, Lirida Alves de Barros Naviner
2023 J jnl
Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition.
IEEE Des. Test
Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Renyuan Zhang, Yu Gong, Zhen Wang, Wei Ge, Jun Yang
2023 — conf
Spice-Compatible Modeling of Double Barrier MTJ for Highly Reliable Circuits.
ICTA
You Wang, Yefan Xu, Chaoyue Zhang, Yu Gong, Hao Cai, Weiqiang Liu
2023 — conf
Temperature-Adaptive MRAM Sensing Using Varied Magneto-Resistance.
ICTA
Jiongzhe Su, Hao Zhang, Hao Cai
2023 — conf
Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing Architecture.
ASP-DAC
Yueting Li, He Zhang, Xueyan Wang, Hao Cai, Yundong Zhang, Shuqin Lv, Renguang Liu, Weisheng Zhao
2023 J jnl
W-AMA: Weight-aware Approximate Multiplication Architecture for neural processing.
Comput. Electr. Eng.
Bo Liu, Renyuan Zhang, Qiao Shen, Zeju Li, Na Xie, Yuanhao Wang, Chonghang Xie, Hao Cai
2023 Misc conf
Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs.
CASES
Xingyu Xu, Qingwen Wei, Yang Zhang, Hao Cai, Bo Liu
2022 — conf
A CGP-based Efficient Approximate Multiplier with Error Compensation.
ICTA
Qiao Shen, Renyuan Zhang, Hao Zhang, Hao Cai, Bo Liu, Jian Xiao
2022 C conf
A Low Power DNN-based Speech Recognition Processor with Precision Recoverable Approximate Computing.
ISCAS
Bo Liu, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Ziyu Wang, Haige Wu, Hao Cai
2022 J jnl
A Machine Learning Attack-Resilient Strong PUF Leveraging the Process Variation of MRAM.
IEEE Trans. Circuits Syst. II Express Briefs
Rashid Ali, Deming Zhang, Hao Cai, Weisheng Zhao, You Wang
2022 — conf
A TWN Inspired Speaker Verification Processor with Hardware-friendly Weight Quantization.
ICTA
Xuanhao Zhang, Haige Wu, Renyuan Zhang, Zihang Xu, Hao Zhang, Bo Liu, Hao Cai
2022 A conf
A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing.
DATE
Bo Liu, Hao Cai, Xuan Zhang, Haige Wu, Anfeng Xue, Zilong Zhang, Zhen Wang, Jun Yang
2022 J jnl
An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bo Liu, Ziyu Wang, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Qiao Shen, Na Xie, Yu Gong, Zhen Wang, Jun Yang, Hao Cai
2022 — ch.
Approximate Computing for Energy-Constrained DNN-Based Speech Recognition.
Approximate Computing
Bo Liu, Hao Cai, Zhen Wang, Jun Yang
2022 J jnl
Bit-error-rate aware sensing-error correction interaction in spintronic MRAM.
J. Syst. Archit.
Hao Cai, Xinfang Tong, Pengcheng Wu, Xinning Liu, Bo Liu
2022 — conf
Low-cost stochastic number generator based on MRAM for stochastic computing.
NANOARCH
You Wang, Bi Wu, Hao Cai, Weiqiang Liu
2022 J jnl
More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Ziyu Wang, Yu Gong, Weiqiang Liu, Jinjiang Yang, Zhen Wang, Jun Yang
2022 J jnl
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang
2022 J jnl
Quality Driven Systematic Approximation for Binary-Weight Neural Network Deployment.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yu Gong, Hao Cai, Haige Wu, Wei Ge, Hao Yan, Zhen Wang, Longxing Shi, Bo Liu
2022 J jnl
Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing.
Sci. China Inf. Sci.
Bo Liu, Zilong Zhang, Hao Cai, Reyuan Zhang, Zhen Wang, Jun Yang
2022 — ch.
Spintronic Solutions for Approximate Computing.
Approximate Computing
You Wang, Hao Cai, Kaili Zhang, Bo Wu, Bo Liu, Deming Zhang, Weisheng Zhao
2022 — conf
Towards Near LLC Speed STT-MRAM Sensing Using Reconfigurable Clock Trimming.
ICTA
Xiaoyun Tian, Zhongjian Bian, Hao Cai
2022 A conf
Triple-Skipping Near-MRAM Computing Framework for AIoT Era.
DATE
Juntong Chen, Hao Cai, Bo Liu, Jun Yang
2022 J jnl
Writing-only in-MRAM computing paradigm for ultra-low power applications.
Microprocess. Microsystems
Bo Liu, Mingyue Liu, Yongliang Zhou, Xiaofeng Hong, Hao Cai, Lirida Alves de Barros Naviner
2021 A conf
A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition.
DATE
Bo Liu, Zeyu Shen, Lepeng Huang, Yu Gong, Zilong Zhang, Hao Cai
2021 J jnl
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS.
IEEE J. Solid State Circuits
Weiwei Shan, Minhao Yang, Tao Wang, Yicheng Lu, Hao Cai, Lixuan Zhu, Jiaming Xu, Chengjun Wu, Longxing Shi, Jun Yang
2021 — conf
A Novel Hybrid Nonvolatile SRAM for Suppressing Leakage Power Using Tunnel FET.
ASICON
Xiaofeng Hong, Hao Cai
2021 J jnl
A survey of in-spin transfer torque MRAM computing.
Sci. China Inf. Sci.
Hao Cai, Bo Liu, Juntong Chen, Lirida A. B. Naviner, Yongliang Zhou, Zhen Wang, Jun Yang
2021 — conf
Analytical Delay Model in Near-Threshold Domain Considering Transition Time.
ICTA
Haiyang Jiang, Bingqian Xu, Peng Cao, Hao Cai
2021 — conf
Cryogenic In-MRAM Computing.
NANOARCH
Yaoru Hou, We Ge, Yanan Guo, Lirida A. B. Naviner, You Wang, Bo Liu, Jun Yang, Hao Cai
2021 — conf
Hybrid MTJ-CMOS Integration for Sigma-Delta ADC.
NANOARCH
Yu-ang Wu, Lirida A. B. Naviner, Hao Cai
2021 — conf
In-MRAM Computing Elements with Single-Step Convolution and Fully Connected for BNN/TNN.
ICTA
Zhong-Jian Bian, Yanan Guo, Bo Liu, Hao Cai
2021 — conf
Modified Peripheral MRAM Sensing for In-memory Boolean Logic.
ASICON
Zhong-Jian Bian, Xiaofeng Hong, Juntong Chen, Hao Cai
2021 J jnl
Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell.
CoRR
Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang
2021 J jnl
Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration.
IEEE Trans. Circuits Syst. II Express Briefs
Hao Cai, Juntong Chen, Yongliang Zhou, Weisheng Zhao
2021 — conf
Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM.
ASICON
You-You Zhang, Lirida A. B. Naviner, Hao Cai
2020 J jnl
A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor.
IEEE Trans. Circuits Syst.
Bo Liu, Hao Cai, Zhen Wang, Yuhao Sun, Zeyu Shen, Wentao Zhu, Yan Li, Yu Gong, Wei Ge, Jun Yang, Longxing Shi
2020 — conf
A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing.
ACM Great Lakes Symposium on VLSI
Bo Liu, Yan Li, Lepeng Huang, Hao Cai, Wentao Zhu, Shisheng Guo, Yu Gong, Zhen Wang
2020 — conf
A Learning-Based Timing Prediction Framework for Wide Supply Voltage Design.
ACM Great Lakes Symposium on VLSI
Wei Bao, Peng Cao, Hao Cai, Aiguo Bu
2020 — conf
A Modeling Attack Resilient Physical Unclonable Function Based on STT-MRAM.
ACM Great Lakes Symposium on VLSI
Zhengyi Hou, You Wang, Deming Zhang, Chengzhi Wang, Hao Cai
2020 J jnl
A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Yongliang Zhou, Hao Cai, Lei Xie, Menglin Han, Mingyue Liu, Shi Xu, Bo Liu, Weisheng Zhao, Jun Yang
2020 — conf
An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN.
ACM Great Lakes Symposium on VLSI
Bo Liu, Yuhao Sun, Hao Cai, Zeyu Shen, Yu Gong, Lepeng Huang, Zhen Wang
2020 C conf
Binarized Weight Neural-Network Inspired Ultra-Low Power Speech Recognition Processor with Time-Domain Based Digital-Analog Mixed Approximate Computing.
ISCAS
Bo Liu, Hao Cai, Yu Gong, Wentao Zhu, Yan Li, Wei Ge, Zhen Wang
2020 J jnl
Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing.
CCF Trans. High Perform. Comput.
Hao Cai, Honglan Jiang, Yongliang Zhou, Menglin Han, Bo Liu
2020 J jnl
MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing.
IEEE Trans. Circuits Syst.
Yongliang Zhou, Hao Cai, Bo Liu, Weisheng Zhao, Jun Yang
2020 J jnl
Magnetic Tunnel Junction Applications.
Sensors
Nilson Maciel, Elaine Crespo Marques, Lirida A. B. Naviner, Yongliang Zhou, Hao Cai
2020 — conf
Magnetic Tunnel Junction-based Analog-to-Digital Converter using Spin Orbit Torque Mechanism.
ICECS
Nilson Maciel, Elaine Crespo Marques, Lírida A. B. Naviner, Hao Cai
2020 J jnl
TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS.
IEEE J. Solid State Circuits
Weiwei Shan, Wentao Dai, Chuan Zhang, Hao Cai, Peiye Liu, Jun Yang, Longxing Shi
2020 J jnl
Towards an automated design flow for memristor based VLSI circuits.
Integr.
Lei Xie, Hao Cai, Chao Wang, Jun Yang
2019 J jnl
A Review of Sparse Recovery Algorithms.
IEEE Access
Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang
2019 — conf
A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement.
NANOARCH
Yongliang Zhou, Menglin Han, Mingyue Liu, Hao Cai, Bo Liu, Jun Yang
2019 J jnl
A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Weiwei Shan, Xinchao Shang, Xing Wan, Hao Cai, Chuan Zhang, Jun Yang
2019 J jnl
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Cai, You Wang, Lirida Alves de Barros Naviner, Xinning Liu, Weiwei Shan, Jun Yang, Weisheng Zhao
2019 — conf
Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM.
NANOARCH
Mingyue Liu, Hao Cai, Menglin Han, Lei Xie, Jun Yang, Lirida A. B. Naviner
2019 C conf
Deep Learning Approaches for Sparse Recovery in Compressive Sensing.
ISPA
Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang
2019 — conf
Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery.
SiPS
Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang
2019 — conf
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction.
ISVLSI
Hao Cai, Honglan Jiang, Menglin Han, Zhaohao Wang, You Wang, Jun Yang, Jie Han, Leibo Liu, Weisheng Zhao
2019 — conf
REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing.
NANOARCH
Lei Xie, Hao Cai, Jun Yang
2019 — conf
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI.
ACM Great Lakes Symposium on VLSI
Hao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang, Weisheng Zhao
2018 — conf
A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.
ISVLSI
Liuyang Zhang, Wang Kang, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial, Weisheng Zhao
2018 J jnl
A high-reliability and low-power computing-in-memory implementation within STT-MRAM.
Microelectron. J.
Liuyang Zhang, Erya Deng, Hao Cai, You Wang, Lionel Torres, Aida Todri-Sanial, Youguang Zhang
2018 — conf
Compressed Sensing for Wideband HF Channel Estimation.
ICFSP
Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang
2018 — conf
Correlation-Based Electromagnetic Analysis Attack Using Haar Wavelet Reconstruction with Low-Pass Filtering on an FPGA Implementaion of AES.
TrustCom/BigDataSE
Aiguo Bu, Wentao Dai, Minyi Lu, Hao Cai, Weiwei Shan
2018 — conf
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.
ACM Great Lakes Symposium on VLSI
You Wang, Yue Zhang, Youguang Zhang, Weisheng Zhao, Hao Cai, Lirida A. B. Naviner
2018 C conf
Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques.
ISCAS
Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Weiwei Shan, Jun Yang, Weisheng Zhao
2018 J jnl
HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wentao Dai, Weiwei Shan, Xinchao Shang, Xinning Liu, Hao Cai, Jun Yang
2018 — conf
MRAM-on-FDSOI Integration: A Bit-Cell Perspective.
ISVLSI
Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao
2018 — conf
Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power.
DCIS
Hao Cai, Menglin Han, You Wang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao
2018 J jnl
Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology.
Microelectron. Reliab.
Nilson Maciel, Elaine Crespo Marques, Lirida A. B. Naviner, Hao Cai
2018 — conf
Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement.
APCCAS
Menglin Han, Hao Cai, Jun Yang, Lirida A. B. Naviner, You Wang, Weisheng Zhao
2017 — conf
Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device.
ACM Great Lakes Symposium on VLSI
Hao Cai, You Wang, Lirida A. B. Naviner, Wang Kang, Weisheng Zhao
2017 — conf
Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core.
ISVLSI
Hao Cai, You Wang, Lirida A. B. Naviner, Weisheng Zhao
2017 J jnl
Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Cai, You Wang, Lirida Alves de Barros Naviner, Weisheng Zhao
2016 — conf
A novel circuit design of true random number generator using magnetic tunnel junction.
NANOARCH
You Wang, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao
2016 J jnl
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.
Microelectron. Reliab.
You Wang, Hao Cai, Lirida A. B. Naviner, Xiaoxuan Zhao, Yue Zhang, Mariem Slimani, Jacques-Olivier Klein, Weisheng Zhao
2016 — conf
Approximate computing in MOS/spintronic non-volatile full-adder.
NANOARCH
Hao Cai, You Wang, Lirida A. B. Naviner, Zhaohao Wang, Weisheng Zhao
2016 J jnl
Efficient reliability evaluation methodologies for combinational circuits.
Microelectron. Reliab.
Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner, You Wang, Mariem Slimani, Jean-François Naviner
2016 J jnl
Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters.
Microelectron. Reliab.
Mariem Slimani, Paulo F. Butzen, Lirida A. B. Naviner, You Wang, Hao Cai
2015 J jnl
A dual-rail compact defect-tolerant multiplexer.
Microelectron. Reliab.
Arwa Ben Dhia, Mariem Slimani, Hao Cai, Lirida A. B. Naviner
2015 J jnl
Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method.
Microelectron. Reliab.
Ting An, Kaikai Liu, Hao Cai, Lirida A. B. Naviner
2015 J jnl
Compact thermal modeling of spin transfer torque magnetic tunnel junction.
Microelectron. Reliab.
You Wang, Hao Cai, Lirida A. B. Naviner, Yue Zhang, Jacques-Olivier Klein, Weisheng Zhao
2015 J jnl
Cross-layer investigation of continuous-time sigma-delta modulator under aging effects.
Microelectron. Reliab.
Hao Cai, You Wang, Kaikai Liu, Lirida Alves de Barros Naviner, Hervé Petit, Jean-François Naviner
2015 — conf
Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction.
NEWCAS
Lirida Alves de Barros Naviner, Hao Cai, You Wang, Weisheng Zhao, Arwa Ben Dhia
2015 J jnl
Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology.
Microelectron. Reliab.
Hao Cai, You Wang, Lirida A. B. Naviner, W. S. Zhao
2014 — conf
Efficient computation of combinational circuits reliability based on probabilistic transfer matrix.
ICICDT
Lirida A. B. Naviner, Kaikai Liu, Hao Cai, Jean-François Naviner
2014 — conf
Efficient implementation for accurate analysis of CED circuits against multiple faults.
MIXDES
Ting An, Kaikai Liu, Hao Cai, Lirida Alves de Barros Naviner
2014 — conf
Reliability-aware delay faults evaluation of CMOS flip-flops.
MIXDES
Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner
2014 — conf
Simulation study of aging in CMOS binary adders.
MIPRO
Ting An, Hao Cai, Lirida Alves de Barros Naviner
2013 — conf
A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts.
NEWCAS
Hao Cai, Hervé Petit, Jean-François Naviner
2013 — conf
A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology.
EUROCON
Kaikai Liu, Ting An, Hao Cai, Lirida A. B. Naviner, Jean-François Naviner, Hervé Petit
2013 — conf
Reliability analysis of combinational circuits with the influences of noise and single-event transients.
DFTS
Kaikai Liu, Hao Cai, Ting An, Lirida A. B. Naviner, Jean-François Naviner, Hervé Petit
2012 J jnl
A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems.
J. Low Power Electron.
Hao Cai, Hervé Petit, Jean-François Naviner
2011 J jnl
Reliability aware design of low power continuous-time sigma-delta modulator.
Microelectron. Reliab.
Hao Cai, Hervé Petit, Jean-François Naviner