Hao-Chiao Hong

40 papers C 8Journal 18Unranked 14
YearRankTypeTitle / Venue / Authors
2025 C conf
A Reference-less All-digital BPSK-based Clock and Data Recovery Circuitry for Die-to-Die Interfaces.
ISCAS
Yi-Ting Yang, Hao-Chiao Hong, Kuo-Hsing Cheng
2024 J jnl
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.
IEEE Trans. Circuits Syst. II Express Briefs
Jian-Wei Su, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024 J jnl
A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Chao-Yu Chen, Yan-Siou Dai, Hao-Chiao Hong
2023 — conf
CMOS MEMS Resonator for Physical Reservoir Computing.
SENSORS
Yi Chiu, Fang-Wei Tsai, Liang-Kai Wang, Yuan-Chieh Lee, Manu Garg, Hao-Chiao Hong
2023 — conf
Parametric Faults in Computing-in-Memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOS.
ITC-Asia
Hao-Chiao Hong, Chien-Hung Chen, Yu-Wun Chen
2022 J jnl
Accurate and Fast On-Wafer Test Circuitry Integrated With a 140-dB-Input-Range Current Digitizer for Parameter Tests in WAT.
IEEE Trans. Circuits Syst. I Regul. Pap.
Long-Yi Lin, Hao-Chiao Hong
2020 J jnl
Interleaved Write Scheme for Improving Sequential Write Throughput of Multi-Chip MLC NAND Flash Memory Systems.
IEEE Trans. Circuits Syst.
Hao-Chiao Hong, Chih-Ko Yang
2019 — conf
A Wireless Gauge Pressure Sensor with Enhanced Sensitivity Fabricated by Flexible PCB Technology For Intracranial Pressure Sensing.
IEEE SENSORS
Yi Chiu, You-Zen Chen, Chia-Chun Hsieh, Hao-Chiao Hong
2019 J jnl
Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao-Chiao Hong, Long-Yi Lin
2019 J jnl
Design of a 0.20-0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao-Chiao Hong, Long-Yi Lin, Yi Chiu
2019 C conf
Multiple Correlation Estimation Based Digital Background Calibration Scheme for Pipelined ADCs.
ISCAS
Kun-Chih Wu, Meng-Shuan Wu, Hao-Chiao Hong
2018 C conf
A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications.
ISCAS
Hao-Chiao Hong, Yi Chiu
2018 C conf
A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation.
ISCAS
Meng-Shuan Wu, Hao-Chiao Hong
2017 — conf
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages.
ATS
Pok Man Preston Law, Cheng-Wen Wu, Long-Yi Lin, Hao-Chiao Hong
2016 — conf
A Study on the Transfer Function Based Analog Fault Model for Linear and Time-Invariant Continuous-Time Analog Circuits.
ATS
Hao-Chiao Hong, Long-Yi Lin
2016 C conf
Gm-C filter with automatic calibration scheme.
DDECS
Hong-Yi Huang, Kun-Yuan Chen, Jia-Hao Xie, Ming-Ta Lee, Hao-Chiao Hong, Kuo-Hsing Cheng
2016 C conf
Low-voltage indoor energy harvesting using photovoltaic cell.
DDECS
Hong-Yi Huang, Shao-Zu Yen, Jhen-Hong Chen, Hao-Chiao Hong, Kuo-Hsing Cheng
2014 J jnl
14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability.
IEEE Trans. Very Large Scale Integr. Syst.
Hao-Chiao Hong, Yung-Shun Chen, Wei-Chieh Fang
2014 — conf
A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits.
VLSI-DAT
Rong-Zhou Kuo, Hao-Chiao Hong
2014 — conf
A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric Vehicles.
ATS
Shao-Feng Hung, Long-Yi Lin, Hao-Chiao Hong
2014 J jnl
A Fully Integrated BIST \(\Delta \Sigma \) ADC Using the In-Phase and Quadrature Waves Fitting Procedure.
IEEE Trans. Instrum. Meas.
Shao-Feng Hung, Hao-Chiao Hong
2014 C conf
A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems.
ISCAS
Yi-Wei Chen, Hao-Chiao Hong
2013 — conf
Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for Verifying the Static Linear Behavior Fault Model.
Asian Test Symposium
Long-Yi Lin, Hao-Chiao Hong
2012 J jnl
A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hao-Chiao Hong
2012 J jnl
Experimental Results of Testing a BIST Σ-Δ ADC on the HOY Wireless Test Platform.
J. Electron. Test.
Shao-Feng Hung, Hao-Chiao Hong
2012 — conf
Testing the Fleischer-Laker switched-capacitor biquad using the diagnosis-after-test procedure.
ISOCC
Shao-Feng Hung, Long-Yi Lin, Hao-Chiao Hong
2011 J jnl
A Digitally Testable Sigma -Delta Modulator Using the Decorrelating Design-for-Digital-Testability.
IEEE Trans. Very Large Scale Integr. Syst.
Sheng-Chuan Liang, Hao-Chiao Hong
2010 J jnl
A Fully Integrated Built-In Self-Test Sigma-Delta ADC Based on the Modified Controlled Sine-Wave Fitting Procedure.
IEEE Trans. Instrum. Meas.
Hao-Chiao Hong, Fang-Yi Su, Shao-Feng Hung
2009 J jnl
A Built-in-Self-Test Sigma-Delta ADC Prototype.
J. Electron. Test.
Hao-Chiao Hong, Sheng-Chuan Liang, Hong-Chin Song
2009 J jnl
A Decorrelating Design-for-Digital-Testability Scheme for Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao-Chiao Hong, Sheng-Chuan Liang
2009 — conf
A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method.
Asian Test Symposium
Shao-Feng Hung, Hao-Chiao Hong, Sheng-Chuan Liang
2008 C conf
A Cost Effective BIST Second-Order Sigma-Delta-Modulator.
DDECS
Hao-Chiao Hong, Sheng-Chuan Liang, Hong-Chin Song
2007 J jnl
A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC.
IEEE J. Solid State Circuits
Hao-Chiao Hong, Guo-Ming Lee
2007 J jnl
A Design-for-Digital-Testability Circuit Structure for Sigma-Delta Modulators.
IEEE Trans. Very Large Scale Integr. Syst.
Hao-Chiao Hong
2007 J jnl
A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators.
J. Electron. Test.
Hao-Chiao Hong
2006 — conf
A Cost Effective Output Response Analyzer for \sum - \delta Modulation Based BIST Systems.
ATS
Hao-Chiao Hong, Sheng-Chuan Liang
2004 — conf
A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose.
Asian Test Symposium
Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng
2004 — conf
Design-for-digital-testability 30 MHz second-order Σ-Δ modulator.
CICC
Hao-Chiao Hong
2003 J jnl
Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems.
IEEE Trans. Circuits Syst. II Express Briefs
Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu, Ding-Ming Kwai
2002 — conf
On-chip Analog Response Extraction with 1-Bit ? - Modulators.
Asian Test Symposium
Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu