Hans Jürgen Mattausch

118 papers B 2C 5Misc 2Journal 59Unranked 49

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Real-Time Surface Identification System for Variable Walking Speeds of Biped Robots. IEEE Embed. Syst. Lett. Aiwen Luo, Sandip Bhattacharya, Mitiko Miura-Mattausch, Yicong Zhou, Hans Jürgen Mattausch
2022	J	`jnl`	Electro-mechanical Model and its Application to biped-robot stability with force Sensors. Int. J. Robotics Autom. Tapas K. Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2021	—	`conf`	Model Development for Robust Design of SOI-MOSFET Circuits used in Radiative Environments. ISDCS Mitiko Miura-Mattausch, Hideyuki Kikuchihara, Hans Jürgen Mattausch
2021	—	`conf`	Modeling of SJ-MOSFET for High-Voltage Applications with Inclusion of Carrier Dynamics during Switching. ISDCS Hideyuki Kikuchihara, Mitiko Miura-Mattausch, Takeshi Mizoguchi, Hajime Nagase, Makoto Hashimoto, Yusuke Kawaguchi, Hans Jürgen Mattausch
2021	J	`jnl`	Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation. IEEE Access Abhishek Kar, Mitiko Miura-Mattausch, Mainak Sengupta, Dondee Navarro, Hideyuki Kikuchihara, Takahiro Iizuka, Hafizur Rahaman, Hans Jürgen Mattausch
2020	J	`jnl`	Analysis of Sensor-Based Real-Time Balancing of Humanoid Robots on Inclined Surfaces. IEEE Access Sunandan Dutta, Tapas Kumar Maiti, Mitiko Miura-Mattausch, Yoshihiro Ochi, Naoto Yorino, Hans Jürgen Mattausch
2020	J	`jnl`	Energy Efficiency of Force-Sensor-Controlled Humanoid-Robot Walking on Indoor Surfaces. IEEE Access Sandip Bhattacharya, Sunandan Dutta, Aiwen Luo, Mitiko Miura-Mattausch, Yoshihiro Ochi, Hans Jürgen Mattausch
2020	J	`jnl`	Force-Sensor-Based Surface Recognition With Surface-Property-Dependent Walking-Speed Adjustment of Humanoid Robot. IEEE Access Sandip Bhattacharya, Aiwen Luo, Sunandan Dutta, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2020	—	`conf`	Force-Sensor-Based Walking-Environment Recognition of Biped Robots. ISDCS Hans Jürgen Mattausch, Aiwen Luo, Sunandan Dutta, Tapas K. Maiti, Mitiko Miura-Mattausch
2020	J	`jnl`	Gyro-Sensor-Based Vibration Control for Dynamic Humanoid-Robot Walking on Inclined Surfaces. Sensors Sunandan Dutta, Mitiko Miura-Mattausch, Yoshihiro Ochi, Naoto Yorino, Hans Jürgen Mattausch
2020	—	`conf`	History Effect on Circuit Performance of SOI-MOSFETs. ISDCS Soumajit Ghosh, Mitiko Miura-Mattausch, Takahiro Iizuka, Hideyuki Kikuchihara, Hafizur Rahaman, Hans Jürgen Mattausch
2020	—	`conf`	Modeling of Short-Channel Effect on Multi-Gate MOSFETs for Circuit Simulation. ISDCS Fernando Ávila Herrera, Mitiko Miura-Mattausch, Takahiro Iizuka, Hideyuki Kikuchihara, Yoko Hirano, Hans Jürgen Mattausch
2020	J	`jnl`	Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model. IEICE Trans. Electron. Kenshiro Sato, Dondee Navarro, Shinya Sekizaki, Yoshifumi Zoka, Naoto Yorino, Hans Jürgen Mattausch, Mitiko Miura-Mattausch
2020	—	`conf`	Surface Recognition and Speed Adjustment of Humanoid Robot Using External Control Circuit. ISDCS Sandip Bhattacharya, Aiwen Luo, Sunandan Dutta, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2019	J	`jnl`	A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier. IEEE Access Aiwen Luo, Fengwei An, Xiangyu Zhang, Hans Jürgen Mattausch
2019	—	`conf`	Analysis of Embedded-Diode Performance in MOSFET under Switching Condition. ISDCS Takao Yamamoto, Yukiya Fukunaga, Daisaku Ikoma, Mitiko Miura-Mattausch, Dondee Navarro, Hans Jürgen Mattausch
2019	—	`conf`	Analysis of IGBT Charging/Discharging Mechanism for Accurate Compact Modeling. ISDCS Yosuke Miyaoku, Mitiko Miura-Mattausch, Akihiro Tone, Hans Jürgen Mattausch, Kai Matsuura, Daisaku Ikoma
2019	—	`conf`	Dynamic Pattern-Recognition-Based Walking-Speed Adjustment for Stable Biped-Robot Movement under Changing Surface Conditions. GCCE Aiwen Luo, Sandip Bhattacharya, Tapas Kumar Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2019	J	`jnl`	Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm. IEICE Trans. Inf. Syst. Jungang Guan, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
2019	C	`conf`	NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data Cache. ICCD Nezam Rohbani, Tapas Kumar Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Hirotaka Takatsuka
2019	—	`conf`	Power Consumption Estimation of Biped Robot During Walking. ISDCS Tapas K. Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Sandip Bhattacharya, Hans Jürgen Mattausch
2019	J	`jnl`	Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values. IEEE Trans. Very Large Scale Integr. Syst. Nezam Rohbani, Hiroaki Gau, Sara Mohammadinejad, Tapas Kumar Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Hirotaka Takatsuka
2019	J	`jnl`	Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs. IEICE Trans. Electron. Arnab Mukhopadhyay, Tapas Kumar Maiti, Sandip Bhattacharya, Takahiro Iizuka, Hideyuki Kikuchihara, Mitiko Miura-Mattausch, Hafizur Rahaman, Sadayuki Yoshitomi, Dondee Navarro, Hans Jürgen Mattausch
2019	—	`conf`	Stability Analysis of Humanoid Robots with Gyro Sensors Subjected to External Push Forces. ISDCS Sunandan Dutta, Tapas K. Maiti, Yoshihiro Ochi, Mitiko Miura-Mattausch, Sandip Bhattacharya, Naoto Yorino, Hans Jürgen Mattausch
2019	J	`jnl`	Surface-Property Recognition With Force Sensors for Stable Walking of Humanoid Robot. IEEE Access Sandip Bhattacharya, Aiwen Luo, Tapas Kumar Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2019	—	`conf`	Validation on Duality in Impact-ionization Carrier Generation at the Onset of Snapback in Power MOSFETs. ISDCS Takahiro Iizuka, Hiroyuki Hashigami, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2018	J	`jnl`	A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space. IEEE Trans. Circuits Syst. Video Technol. Fengwei An, Xiangyu Zhang, Aiwen Luo, Lei Chen, Hans Jürgen Mattausch
2018	J	`jnl`	A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization. IEEE Trans. Circuits Syst. I Regul. Pap. Xiangyu Zhang, Fengwei An, Lei Chen, Idaku Ishii, Hans Jürgen Mattausch
2018	—	`conf`	Compact Modeling for Power Efficient Circuit Design. ESSDERC Mitiko Miura-Mattausch, Hideyuki Kikuchihara, Tahahiro Kajiwara, Yuta Tanimoto, Atsushi Saito, Takahiro Iizuka, Dondee Navarro, Hans Jürgen Mattausch
2018	J	`jnl`	Compact modeling of dynamic trap density evolution for predicting circuit-performance aging. Microelectron. Reliab. Mitiko Miura-Mattausch, Hidenori Miyamoto, Hideyuki Kikuchihara, Tapas K. Maiti, Nezam Rohbani, Dondee Navarro, Hans Jürgen Mattausch
2018	—	`conf`	Fast Recognition and Control of Walking Mode for Humanoid Robot Based on Pressure Sensors and Nearest Neighbor Search. ISPACS Sandip Bhattacharya, Aiwen Luo, Tapas K. Maiti, Sunandan Dutta, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2018	J	`jnl`	Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Aiwen Luo, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
2018	—	`conf`	Self-controlled walking robot with gyro sensor network for stable movement on non-smooth surfaces. SIMPAR Sunandan Dutta, Tapas K. Maiti, Yoshihiro Ochi, Mitiko Miura-Mattausch, Sandip Bhattacharya, Dondee Navarro, Naoto Yorino, Hans Jürgen Mattausch
2017	—	`conf`	Compact modeling approach for electro-mechanical system simulation. ASICON Tapas K. Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2017	J	`jnl`	Modeling of Field-Plate Effect on Gallium-Nitride-Based High Electron Mobility Transistors for High-Power Applications. IEICE Trans. Electron. Takeshi Mizoguchi, Toshiyuki Naka, Yuta Tanimoto, Yasuhiro Okada, Wataru Saito, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2017	—	`conf`	Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits. ESSDERC Mitiko Miura-Mattausch, Hidenori Miyamoto, Hideyuki Kikuchihara, Dondee Navarro, Tapas K. Maiti, Nezam Rohbani, C. Ma, Hans Jürgen Mattausch, A. Schiffmann, Alexander Steinmair, Ehrenfried Seebacher
2017	J	`jnl`	Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures. Sensors Jungang Guan, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
2016	J	`jnl`	A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration. IEEE Trans. Multi Scale Comput. Syst. Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
2016	J	`jnl`	Actuator-Control Circuit Based on OTFTs and Flow-Rate Estimation for an All-Organic Fluid Pump. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Lei Chen, Tapas Kumar Maiti, Hidenori Miyamoto, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2016	C	`conf`	Dynamically reconfigurable system for LVQ-based on-chip learning and recognition. ISCAS Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
2016	J	`jnl`	Efficiency Analysis of SiC-MOSFET-Based Bidirectional Isolated DC/DC Converters. IEICE Trans. Electron. Atsushi Saito, Kenshiro Sato, Yuta Tanimoto, Kai Matsuura, Yutaka Sasaki, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Yoshifumi Zoka
2016	—	`conf`	Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction. APCCAS Yuki Fujita, Fengwei An, Aiwen Luo, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
2016	J	`jnl`	k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching. IEICE Trans. Electron. Fengwei An, Lei Chen, Toshinobu Akazawa, Shogo Yamazaki, Hans Jürgen Mattausch
2015	—	`conf`	Mixed-domain compact modeling framework for fluid flow driven by electrostatic organic actuators. ESSDERC Tapas Kumar Maiti, Lei Chen, Hidenori Miyamoto, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2015	—	`conf`	Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors. A-SSCC Fengwei An, Keisuke Mihara, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch
2014	—	`conf`	A SoPC architecture for nearest-neighbor based learning and recognition. ISPACS Fengwei An, Lei Chen, Hans Jürgen Mattausch
2014	—	`conf`	A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability. CICC Fengwei An, Toshinobu Akazawa, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch
2014	J	`jnl`	Compact Modeling of Injection Enhanced Insulated Gate Bipolar Transistor Valid for Optimization of Switching Frequency. IEICE Trans. Electron. Takao Yamamoto, Masataka Miyake, Uwe Feldmann, Hans Jürgen Mattausch, Mitiko Miura-Mattausch
2014	—	`conf`	LVQ neural network SoC adaptable to different on-chip learning and recognition applications. APCCAS Fengwei An, Toshinobu Akazawa, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch
2014	J	`jnl`	Memory-based hardware-accelerated system for high-speed human detection. Adv. Robotics Indra Bagus Wicaksono, Fengwei An, Hans Jürgen Mattausch
2013	J	`jnl`	K-means clustering algorithm for multimedia applications with flexible HW/SW co-design. J. Syst. Archit. Fengwei An, Hans Jürgen Mattausch
2013	J	`jnl`	Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias Conditions. IEICE Trans. Electron. Chenyue Ma, Hans Jürgen Mattausch, Masataka Miyake, Takahiro Iizuka, Kazuya Matsuzawa, Seiichiro Yamaguchi, Teruhiko Hoshida, Akinori Kinoshita, Takahiko Arakawa, Jin He, Mitiko Miura-Mattausch
2013	J	`jnl`	Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation. IEICE Trans. Electron. Takahiro Iizuka, Kenji Fukushima, Akihiro Tanaka, Hideyuki Kikuchihara, Masataka Miyake, Hans Jürgen Mattausch, Mitiko Miura-Mattausch
2013	—	`conf`	Word-parallel coprocessor architecture for digital nearest Euclidean distance search. ESSCIRC Toshinobu Akazawa, Seiryu Sasaki, Hans Jürgen Mattausch
2012	J	`jnl`	A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching. IEICE Trans. Inf. Syst. Fengwei An, Tetsushi Koide, Hans Jürgen Mattausch
2012	J	`jnl`	Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping. IEEE J. Solid State Circuits Hans Jürgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi Koide
2012	C	`conf`	Cluster-Based Prototype Learning System for Multiple Applications with Flexible HW/SW Codesign. PDCAT Fengwei An, Hans Jürgen Mattausch
2012	J	`jnl`	Compact Modeling of Expansion Effects in LDMOS. IEICE Trans. Electron. Takahiro Iizuka, Takashi Sakuda, Yasunori Oritsuki, Akihiro Tanaka, Masataka Miyake, Hideyuki Kikuchihara, Uwe Feldmann, Hans Jürgen Mattausch, Mitiko Miura-Mattausch
2012	—	`conf`	Digital associative memory for word-parrallel Manhattan-distance-based vector quantization. ESSCIRC Seiryu Sasaki, Masahiro Yasuda, Hans Jürgen Mattausch
2012	—	`conf`	Human recognition with a hardware-accelerated multi-prototype learning and classification system. ROBIO Indra Bagus Wicaksono, Fengwei An, Hans Jürgen Mattausch
2011	J	`jnl`	A Scalable Massively Parallel Processor for Real-Time Image Processing. IEEE J. Solid State Circuits Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
2011	J	`jnl`	An associative memory-based learning model with an efficient hardware implementation in FPGA. Expert Syst. Appl. Ali Ahmadi, Hans Jürgen Mattausch, Md. Anwarul Abedin, Mahmoud Saeidi, Tetsushi Koide
2011	J	`jnl`	Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design. IEICE Trans. Electron. Norio Sadachika, Shu Mimura, Akihiro Yumisaki, Koh Johguchi, Akihiro Kaya, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
2011	—	`conf`	Real-time hybrid learning and recognition system with software-hardware cooperation. ROBIO Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide
2011	J	`jnl`	Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems. IEICE Trans. Inf. Syst. Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Masaharu Tagami, Masakatsu Ishizaki
2010	—	`conf`	A scalable massively parallel processor for real-time image processing. ISSCC Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
2010	Misc	`conf`	Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size. ICNC Tetsushi Koide, R. Kimura, T. Sugahara, K. Okazaki, Hans Jürgen Mattausch
2010	—	`conf`	Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping. ESSCIRC Hans Jürgen Mattausch, Wataru Imafuku, Tania Ansari, Akio Kawabata, Tetsushi Koide
2010	J	`jnl`	Measurement-Based Ring Oscillator Variation Analysis. IEEE Des. Test Comput. Koh Johguchi, Akihiro Kaya, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide, Norio Sadachika
2010	Misc	`conf`	Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding. ICNC Akio Kawabata, Tetsushi Koide, Hans Jürgen Mattausch
2009	J	`jnl`	Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors. IEICE Trans. Electron. Masataka Miyake, Daisuke Hori, Norio Sadachika, Uwe Feldmann, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shunsuke Miyamoto
2009	J	`jnl`	Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation. IEICE Trans. Electron. Masataka Miyake, Daisuke Hori, Norio Sadachika, Uwe Feldmann, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Takahiro Iizuka, Kazuya Matsuzawa, Yasuyuki Sahara, Teruhiko Hoshida, Toshiro Tsukada
2008	J	`jnl`	Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization. IEICE Trans. Electron. Norio Sadachika, Takahiro Murakami, Hideki Oka, Ryou Tanabe, Hans Jürgen Mattausch, Mitiko Miura-Mattausch
2008	J	`jnl`	Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Trans. Electron. Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2008	J	`jnl`	Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations. Math. Comput. Simul. Tatsuya Ezaki, Dondee Navarro, Youichi Takeda, Norio Sadachika, Gaku Suzuki, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto
2008	—	`book`	The Physics and Modeling of Mosfets - Surface-Potential Model HiSIM Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ezaki
2007	J	`jnl`	4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Trans. Electron. Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka
2007	—	`conf`	A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. ESSCIRC Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide
2007	J	`jnl`	A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin. IEICE Electron. Express Koh Johguchi, Yuya Mukuda, Ken-ichi Aoyama, Hans Jürgen Mattausch, Tetsushi Koide
2007	J	`jnl`	Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Trans. Inf. Syst. Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007	C	`conf`	Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007	J	`jnl`	Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Trans. Inf. Syst. Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007	J	`jnl`	Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Shogo Sakakibara, Tetsushi Koide, Hans Jürgen Mattausch
2007	J	`jnl`	Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory. IEICE Trans. Inf. Syst. Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch
2006	B	`conf`	A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA. IEEE Congress on Evolutionary Computation Ali Ahmadi, M. Arifin Ritonga, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide
2006	J	`jnl`	A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Trans. Electron. Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto
2006	—	`conf`	An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. APCCAS Takashi Morimoto, Hidekazu Adachi, Kousuke Yamaoka, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch
2006	—	`conf`	Application of Multi-ported CAM for Parallel Coding. APCCAS Takeshi Kumaki, Y. Kouno, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch
2006	J	`jnl`	Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation. IEICE Trans. Inf. Syst. Takashi Morimoto, Hidekazu Adachi, Osamu Kiriyama, Tetsushi Koide, Hans Jürgen Mattausch
2006	—	`conf`	Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. APCCAS Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Tetsushi Koide, Hans Jürgen Mattausch
2006	—	`conf`	Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. ASP-DAC Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch
2006	C	`conf`	Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. ISCAS Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch
2006	—	`conf`	Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa
2005	J	`jnl`	1/ IEICE Trans. Electron. Shizunori Matsumoto, Hiroaki Ueno, Satoshi Hosokawa, Toshihiko Kitamura, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
2005	J	`jnl`	A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Trans. Electron. Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide
2005	J	`jnl`	A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. IEICE Trans. Electron. Dondee Navarro, Takeshi Mizoguchi, Masami Suetake, Kazuya Hisamitsu, Hiroaki Ueno, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
2005	J	`jnl`	A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	—	`conf`	A low-power video segmentation LSI with boundary-active-only architecture. ASP-DAC Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch
2005	B	`conf`	A parallel hardware design for parametric active contour models. AVSS Ali Ahmadi, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide
2005	—	`conf`	CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2005	J	`jnl`	Chip size and performance evaluations of shared cache for on-chip multiprocessor. Syst. Comput. Jpn. Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide
2005	—	`conf`	Design of superscalar processor with multi-bank register file. ISCAS (4) Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch
2005	J	`jnl`	Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	—	`conf`	MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime. CICC Youichi Takeda, Dondee Navarro, Shingo Chiba, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto
2005	—	`conf`	Object tracking in video pictures based on image segmentation and pattern matching. ISCAS (4) Takashi Morimoto, Osamu Kiriyama, Yohmei Harada, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch
2004	—	`conf`	350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. ASP-DAC Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch
2004	—	`conf`	Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. ASP-DAC Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch
2004	—	`conf`	Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ASP-DAC Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka
2004	J	`jnl`	Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation. IEICE Trans. Inf. Syst. Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch
2003	—	`conf`	A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. ASP-DAC Tetsushi Koide, Hans Jürgen Mattausch, Yuji Yano, Takayuki Gyohten, Yoshihiro Soda
2003	—	`conf`	A novel hierarchical multi-port cache. ESSCIRC Zhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Tetsuo Hironaka
2003	—	`conf`	Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design. ASP-DAC Kazuya Hisamitsu, Hiroaki Ueno, Masayasu Tanaka, Daisuke Kitamaru, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
2002	J	`jnl`	Circuit Simulation Models for Coming MOSFET Generations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mitiko Miura-Mattausch, Hiroaki Ueno, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
2002	J	`jnl`	Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance. IEEE J. Solid State Circuits Hans Jürgen Mattausch, Takayuki Gyohten, Yoshihiro Soda, Tetsushi Koide
2001	—	`conf`	Correlation method of circuit-performance and technology fluctuations for improved design reliability. ASP-DAC D. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
2001	—	`conf`	Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability. CICC Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Y. Tatsumi, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Terufumi Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
2000	—	`conf`	High performance of short-channel MOSFETs due to an elevated central-channel doping. ASP-DAC Masayasu Tanaka, N. Tokida, T. Okagaki, Mitiko Miura-Mattausch, Walter Hansch, Hans Jürgen Mattausch
1988	J	`jnl`	A memory-based high-speed digital delay line with a large adjustable length. IEEE J. Solid State Circuits Hans Jürgen Mattausch, Fred Matthiesen, Jutta Hartl, Reinhard Tielert, Erwin P. Jacobs