Hans Eveking - RankMe

29 papers A* 2A 1B 1C 4Journal 2Unranked 16

Year	Rank	Type	Title / Venue / Authors
2011	—	`conf`	Analyse von Gegenbeispielen bei Verifikation mit unvollständigen Eigenschaftssätzen. MBMV Tobias Dornes, Martin Schweikert, Hans Eveking
2011	—	`conf`	Erzeugung von Operationseigenschaften aus UML Sequenzdiagrammen. MBMV Martin Schweikert, Tobias Dornes, Hans Eveking
2011	—	`conf`	Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. HLDVT Hans Eveking, Tobias Dornes, Martin Schweikert
2010	—	`conf`	Formale Verifikation von Systemeigenschaften unter Verwendung normalisierter formaler Spezifikationen. MBMV Tobias Dornes, Hans Eveking
2010	—	`conf`	Verwendung von UML Sequenzdiagrammen zur Spezifikation und Generierung von RTL Eigenschaftssätzen. MBMV Martin Schweikert, Hans Eveking
2009	—	`conf`	Quantitative Qualitätsaussagen über Testbenches mittels formaler Eigenschaften. MBMV Martin Oberkönig, Martin Schickel, Hans Eveking
2008	—	`conf`	Eine quantitative Vollständigkeitsanalyse für Eigenschaftssätze. MBMV Martin Oberkönig, Martin Schickel, Hans Eveking
2007	C	`conf`	A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set. FDL Martin Schickel, Martin Oberkönig, Martin Schweikert, Hans Eveking
2007	B	`conf`	A Quantitative Completeness Analysis for Property-Sets. FMCAD Martin Oberkönig, Martin Schickel, Hans Eveking
2007	—	`conf`	Methoden zur Verifikation von Kommunikationsstrukturen. MBMV Martin Braun, Minh D. Nguyen, Hans Eveking, Martin Schickel, Wolfgang Kunz
2007	C	`conf`	Multi-Level Assertion-Based Design. MEMOCODE Hans Eveking, Martin Braun, Martin Schickel, Martin Schweikert, Volker Nimbler
2006	C	`conf`	On Consistency and Completeness of Property-Sets. FDL Martin Schickel, Volker Nimbler, Martin Braun, Hans Eveking
2006	—	`ed.`	VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany VLSI-SoC (Selected Papers) Manfred Glesner, Ricardo Augusto da Luz Reis, Leandro Soares Indrusiak, Vincent John Mooney III, Hans Eveking
2003	C	`ed.`	IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003 VLSI-SoC Manfred Glesner, Ricardo Augusto da Luz Reis, Hans Eveking, Vincent John Mooney III, Leandro Soares Indrusiak, Peter Zipf
2001	J	`jnl`	Formale Verifikationsverfahren (Formal Verification). Informationstechnik Tech. Inform. Hans Eveking
2001	—	`conf`	Symbolic simulation techniques-state-of-the-art and applications. HLDVT Claudia Blank, Hans Eveking, Jens Levihn, Gerd Ritter
2000	—	`conf`	Formale Verifikation der Register-Allokation. MBMV Claudia Blank, Gerd Ritter, Holger Hinrichsen, Hans Eveking
1999	A	`conf`	Automatic Verification of Scheduling Results in High-Level Synthesis. DATE Hans Eveking, Holger Hinrichsen, Gerd Ritter
1999	—	`conf`	Automatische Synthese und Verifikation von RISC-Prozessoren. MBMV Holger Hinrichsen, Gerd Ritter, Hans Eveking
1999	—	`conf`	Formal Verification of Descriptions with Distinct Order of Memory Operations. ASIAN Gerd Ritter, Holger Hinrichsen, Hans Eveking
1999	—	`conf`	Formal Verification of Designs with Complex Control by Symbolic Simulation. CHARME Gerd Ritter, Hans Eveking, Holger Hinrichsen
1995	—	`ed.`	Correct Hardware Design and Verification Methods, IFIP WG 10.5 Advanced Research Working Conference, CHARME '95, Frankfurt/Main, Germany, October 2-4, 1995, Proceedings CHARME Paolo Camurati, Hans Eveking
1994	—	`conf`	(V)HDL-based verification of heterogeneous synchronous/asynchronous systems. EURO-DAC Hans Eveking
1993	A*	`conf`	Optimization and Resynthesis of Complex Data-Paths. DAC Hans Eveking, Stefan Höreth
1991	—	`book`	Verifikation digitaler Systeme - eine Einführung in den Entwurf korrekter digitaler Systeme. Hans Eveking
1990	A*	`conf`	Automatic Verification of Extensions of Hardware Descriptions. CAV Hans Eveking
1990	—	`conf`	Automatic Verification of Extensions of Hardware Descriptions. CAV (DIMACS/AMS volume) Hans Eveking
1990	—	`conf`	Formal verification of timing conditions. EURO-DAC Hans Eveking, Christoph Mai
1987	J	`jnl`	Formal reasoning about switch-level MOS descriptions. Microprocess. Microprogramming Hans Eveking