Hans-Jörg Pfleiderer

41 papers A 1B 7C 4Journal 11Unranked 18

Year	Rank	Type	Title / Venue / Authors
2009	—	`conf`	Fully programmable layered LDPC decoder architecture. EUSIPCO Christiane Beuschel, Hans-Jörg Pfleiderer
2009	B	`conf`	Numerically controlled oscillators using linear approximation. FPL Hans-Jörg Pfleiderer, Stefan Lachowicz
2008	—	`conf`	Configurable Blocks for Multi-precision Multiplication. DELTA Oliver A. Pfänder, Reinhard Nopper, Hans-Jörg Pfleiderer, Shun Zhou, Amine Bermak
2008	B	`conf`	EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs. FPL Oliver A. Pfänder, Hans-Jörg Pfleiderer
2008	B	`conf`	FPGA implementation of a flexible decoder for long LDPC codes. FPL Christiane Beuschel, Hans-Jörg Pfleiderer
2008	—	`conf`	Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA. DELTA Stefan Lachowicz, Hans-Jörg Pfleiderer
2007	—	`conf`	A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier. ICECS Shun Zhou, Oliver A. Pfänder, Hans-Jörg Pfleiderer, Amine Bermak
2007	C	`conf`	Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA. ISCAS Christophe Layer, Daniel Schaupp, Hans-Jörg Pfleiderer
2007	C	`ed.`	VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia VLSI-SoC Ricardo Augusto da Luz Reis, Adam Osseiran, Hans-Jörg Pfleiderer
2006	B	`conf`	Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. FPL Francisco-Javier Veredas, Hans-Jörg Pfleiderer
2006	—	`conf`	Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. DATE Designers' Forum Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer
2006	C	`conf`	LUT-based MPGAs for fast turnaround time conversion flow. ISCAS Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer
2006	—	`conf`	Power estimation of a LUT-based MPGA. FPT Francisco-Javier Veredas, Hans-Jörg Pfleiderer
2006	—	`conf`	Regular Routing Architecture for a LUT-based MPGA. ISVLSI Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer
2006	J	`jnl`	Self-calibrating microphone arrays for speech signal acquisition: A systematic approach. Signal Process. Markus Buck, Tim Haulick, Hans-Jörg Pfleiderer
2006	—	`conf`	Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations. PATMOS Jürgen Rauscher, Hans-Jörg Pfleiderer
2005	J	`jnl`	3D Chip Stack Technology Using Through-Chip Interconnects. IEEE Des. Test Comput. Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher
2005	—	`conf`	An Interactive Systemc Course Featuring Real-Time Online Compiling and Analysis. EDUTECH Oliver A. Pfänder, Christophe Layer, Wolfgang Schlecker, Hans-Jörg Pfleiderer
2005	J	`jnl`	Comprehensive pharmacokinetic model of insulin Glargine and other insulin formulations. IEEE Trans. Biomed. Eng. Cristina Tarín, Edgar Teufel, Jesús Picó, Jorge Bondia, Hans-Jörg Pfleiderer
2005	A	`conf`	Efficient Hardware Search Engine for Associative Content Retrieval of Long Queries in Huge Multimedia Databases. ICME Christophe Layer, Hans-Jörg Pfleiderer
2005	—	`conf`	Vertical Sorting Techniques Accelerating Associative Accesses based Information Retrieval Systems. Parallel and Distributed Computing and Networks Christophe Layer, Hans-Jörg Pfleiderer
2004	B	`conf`	A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays. FPL Oliver A. Pfänder, Roland Hacker, Hans-Jörg Pfleiderer
2004	B	`conf`	A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data. FPL Christophe Layer, Hans-Jörg Pfleiderer
2004	—	`conf`	A scalable compact architecture for the computation of integer binary logarithms through linear approximation. ISCAS (2) Christophe Layer, Hans-Jörg Pfleiderer, Christoph Heer
2004	—	`conf`	Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures. PATMOS Markus Tahedl, Hans-Jörg Pfleiderer
2004	—	`conf`	High Performance Associative Coprocessor Architecture for Advanced Database Searching. Databases and Applications Christophe Layer, Hans-Jörg Pfleiderer
2003	—	`conf`	A driver load model for capacitive coupled on-chip interconnect buses. SoC Markus Tahedl, Hans-Jörg Pfleiderer
2003	—	`conf`	Modelling the glucose metabolism with backpropagation through time trained Elman nets. NNSP Edgar Teufel, Marco Kletting, Werner G. Teich, Hans-Jörg Pfleiderer, C. Tarin-Sauer
2002	J	`jnl`	Design and Implementation of Discrete Event Control Systems: A Petri Net Based Hardware Approach. Discret. Event Dyn. Syst. Slavek Bulach, Anton Brauchle, Hans-Jörg Pfleiderer, Zdenek Kucerovsky
2002	B	`conf`	Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks. FPL Wolfgang Schlecker, Achim Engelhart, Werner G. Teich, Hans-Jörg Pfleiderer
2001	—	`conf`	Petri Net Based Design and Implementation Methodology for Discrete Event Control Systems. ICATPN Slavek Bulach, Anton Brauchle, Hans-Jörg Pfleiderer, Zdenek Kucerovsky
1999	—	`conf`	Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI. VLSI Stefan Lachowicz, Kamran Eshraghian, Hans-Jörg Pfleiderer
1999	—	`conf`	Self-timed MESFET gallium arsenide circuit techniques for a direct digital frequency synthesiser. ISSPA Stefan Lachowicz, Kamran Eshraghian, M. Hollreiser, Hans-Jörg Pfleiderer
1996	J	`jnl`	Large bandwidth BiCMOS operational amplifiers for SC video applications. IEEE J. Solid State Circuits Gerhard Nebel, Ulrich Kleine, Hans-Jörg Pfleiderer
1995	J	`jnl`	An ECL to CMOS level converter with complementary bipolar output stage. IEEE J. Solid State Circuits Martin Rau, Hans-Jörg Pfleiderer
1995	J	`jnl`	Symbolic pole/zero calculation using SANTAFE. IEEE J. Solid State Circuits Gerhard Nebel, Ulrich Kleine, Hans-Jörg Pfleiderer
1994	C	`conf`	Large Bandwidth BiCMOS Operational Amplifiers for SC-Video-Applications. ISCAS Gerhard Nebel, Ulrich Kleine, Hans-Jörg Pfleiderer
1989	J	`jnl`	A very-high-slew-rate CMOS operational amplifier. IEEE J. Solid State Circuits R. Klinke, Bedrich J. Hosticka, Hans-Jörg Pfleiderer
1985	J	`jnl`	VLSI - Auswirkungen auf konventionelle Rechnerstrukturen. Inform. Spektrum Egon Hörbst, H. Oechslein, Hans-Jörg Pfleiderer
1983	J	`jnl`	A function-independent self-test for large programmable logic arrays. Integr. G. Grassl, Hans-Jörg Pfleiderer
1979	J	`jnl`	Antialiasing Filter with an Improved S/N Ratio. IEEE Trans. Commun. Hans-Jörg Pfleiderer, Karl Knauer