Hanpei Koike

46 papers A* 2A 5C 1Journal 14Unranked 24
YearRankTypeTitle / Venue / Authors
2026 J jnl
Cryogenic CMOS Microwave Signal Selector Using Dual-Stage Injection-Locked Oscillator for Frequency-Multiplexed Qubit Control System.
IEEE J. Solid State Circuits
Hiroshi Fuketa, Ippei Akita, Hanpei Koike, Takahiro Mori
2023 J jnl
A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori
2022 — conf
A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution.
VLSI Technology and Circuits
Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori
2020 J jnl
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping.
Integr.
Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike
2018 J jnl
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device.
IEICE Trans. Inf. Syst.
Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike
2016 C conf
Implementation of pseudo linear feedback shift register physical unclonable function on silicon.
ISCAS
Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike
2016 J jnl
Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology.
IEICE Trans. Inf. Syst.
Masakazu Hioki, Hanpei Koike
2015 J jnl
Impacts of flexible
IEICE Electron. Express
Yasuhiro Ogasahara, Tadashi Nakagawa, Toshihiro Sekigawa, Toshiyuki Tsutsumi, Hanpei Koike
2015 — conf
Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests.
GCCE
Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike
2013 A conf
Fully-functional FPGA prototype with fine-grain programmable body biasing.
FPGA
Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Hanpei Koike, Yohei Matsumoto, Takashi Kawanami, Toshiyuki Tsutsumi
2012 J jnl
A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology.
IEICE Trans. Electron.
Shin-ichi O'Uchi, Kazuhiko Endo, Takashi Matsukawa, Yongxun Liu, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara
2012 J jnl
High-Frequency Precise Characterization of Intrinsic FinFET Channel.
IEICE Trans. Electron.
Hideo Sakai, Shin-ichi O'Uchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara, Hiroki Ishikuro
2010 — conf
0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits.
ESSCIRC
Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara
2010 — conf
Development of a CAD tool for 3D-FPGAs.
3DIC
Naoto Miyamoto, Yohei Matsumoto, Hanpei Koike, Tadayuki Matsumura, Kenichi Osada, Yaoko Nakagawa, Tadahiro Ohmi
2010 — conf
Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET.
CICC
Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara
2009 — conf
High-speed low-power FinFET based domino logic.
ASP-DAC
Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee
2008 J jnl
FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction.
IEICE Trans. Electron.
Shin-ichi O'Uchi, Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki
2008 J jnl
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations.
ACM Trans. Reconfigurable Technol. Syst.
Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa
2007 — conf
A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip.
FPT
Masakazu Hioki, Takashi Kawanami, Yohei Matsumoto, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Toshiyuki Tsutsumi
2007 — conf
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology.
CICC
Shin-ichi O'Uchi, Meishoku Masahara, Kunihiro Sakamoto, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki
2007 J jnl
Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA.
IEICE Trans. Inf. Syst.
Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
2007 A conf
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations.
FPGA
Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
2006 A conf
Evaluation of granularity on threshold voltage control in flex power FPGA.
FPGA
Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
2006 — conf
Evaluation of granularity on threshold voltage control in flex power FPGA.
FPT
Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
2006 A conf
FPGAs with multidimensional mesh topology.
FPGA
Yohei Matsumoto, Hanpei Koike, Akira Masaki
2006 — conf
Optimal set of body bias voltages for an FPGA with field-programmable V
FPT
Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
2005 — conf
XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together.
CICC
Hanpei Koike, Toshihiro Sekigawa
2004 J jnl
Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity.
IEICE Trans. Inf. Syst.
Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
2004 A conf
Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity.
FPGA
Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
1998 A* conf
Fast Speculative Search Engine on the Highly Parallel Computer EM-X.
SIGIR
Hayato Yamana, Hanpei Koike, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi
1997 — conf
Parallel Execution of Radix Sort Program Using Fine-Grain Communication.
IEEE PACT
Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi
1994 — conf
A Fleng Compiler for PIE64.
IFIP PACT
Hidemoto Nakada, Takuya Araki, Hanpei Koike, Hidehiko Tanaka
1994 — conf
A Performance Debugger for a Parallel Logic Programming Language Fleng.
Theory and Practice of Parallel Programming
Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka
1994 J jnl
Architecture of parallel management kernel for PIE64.
Future Gener. Comput. Syst.
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
1993 — conf
Control and Data Flow Visualization for Parallel Logic Programs on a Multi-window Debugger HyperDEBU.
PARLE
Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka
1993 A* conf
Multiple Threads in Cyclic Register Windows.
ISCA
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
1993 — conf
The Instruction Set Architecture of the Inference Processor UNIRED II.
Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka
1993 J jnl
UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64.
New Gener. Comput.
Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka
1992 — conf
Architecture of Parallel Management Kernel for PIE64.
PARLE
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
1992 — conf
HyperDEBU: A Multiwindow Debugger for Parallel Logic Programs.
Programming Environments for Parallel Computing
Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka
1992 — conf
UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64.
FGCS
Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka
1991 — conf
A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages.
ISLP
Yasuo Hidaka, Hanpei Koike, Jun'ichi Tatemura, Hidehiko Tanaka
1989 — conf
Distributed Garbage Collection for the Parallel Inference Engine PIE64.
NACLP
Lu Xu, Hanpei Koike, Hidehiko Tanaka
1989 — conf
Distributed Garbage Collection for the Parallel Inference Machine PIE64.
IFIP Congress
Lu Xu, Hanpei Koike, Hidehiko Tanaka
1988 — conf
Multi-Context Processing and Data Balancing Mechanism of the Parallel Inference Machine PIE64.
FGCS
Hanpei Koike, Hidehiko Tanaka
1986 — conf
Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting.
LP
Hanpei Koike, Hidehiko Tanaka