Hannah Honghua Yang

26 papers A* 1A 3Misc 2Journal 12Unranked 6
YearRankTypeTitle / Venue / Authors
2016 — ch.
Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach.
Encyclopedia of Algorithms
Martin D. F. Wong, Hannah Honghua Yang
2008 — ch.
Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach.
Encyclopedia of Algorithms
Hannah Honghua Yang, Martin D. F. Wong
2007 J jnl
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2007 J jnl
MB
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang
2006 J jnl
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration.
ACM Trans. Design Autom. Electr. Syst.
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani
2006 J jnl
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2006 — conf
Integrating dynamic thermal via planning with 3D floorplanning algorithm.
ISPD
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2005 Misc conf
A Theoretical Upper Bound for IP-Based Floorplanning.
COCOON
Guowu Yang, Xiaoyu Song, Hannah Honghua Yang, Fei Xie
2005 — conf
Microarchitecture evaluation with floorplanning and interconnect pipelining.
ASP-DAC
Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong
2004 J jnl
Constrained floorplanning using network flows.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang
2004 — conf
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.
ISCAS (5)
Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu
2003 — conf
Constrained "Modern" Floorplanning.
ISPD
Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang
2003 J jnl
Integrated floorplanning with buffer/channel insertion for bus-based designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani
2003 A* conf
Multilevel floorplanning/placement for large-scale modules using B*-trees.
DAC
Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang
2002 — conf
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.
ISPD
Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani
2001 — conf
Faster and more accurate wiring evaluation in interconnect-centric floorplanning.
ACM Great Lakes Symposium on VLSI
Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang
2001 J jnl
On extending slicing floorplan to handle L/T-shaped modules andabutment constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
2000 J jnl
Slicing floorplans with range constraint.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
1999 A conf
Integrated floorplanning and interconnect planning.
ICCAD
Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
1999 Misc conf
Logic Verification of Very Large Circuits Using Shark.
VLSI Design
Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman
1999 J jnl
Slicing floorplans with boundary constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
1998 J jnl
Optimal min-area min-cut replication in partitioned circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hannah Honghua Yang, Martin D. F. Wong
1997 J jnl
Circuit clustering for delay minimization under area and pin constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hannah Honghua Yang, Martin D. F. Wong
1996 J jnl
Balanced partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hannah Honghua Yang, Martin D. F. Wong
1995 A conf
New algorithms for min-cut replication in partitioned circuits.
ICCAD
Hannah Honghua Yang, D. F. Wong
1994 A conf
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs.
ICCAD
Hannah Honghua Yang, D. F. Wong