Hanho Lee - RankMe

116 papers A 1C 22Misc 3Journal 53Unranked 37

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Survey and Review on the BFV Homomorphic Encryption Hardware Architecture Implementations. IEEE Access Ardianto Satriawan, Rella Mareta, Hanho Lee
2026	J	`jnl`	NIST Post-Quantum Cryptography Standards: A Comprehensive Review of Theoretical Foundations and Implementations. IEEE Access Quang Dang Truong, Hien Nguyen, Tuy Tan Nguyen, Hanho Lee
2025	C	`conf`	An Efficient NTT-Based Polynomial Multiplication Architecture for BFV Homomorphic Encryption. ISCAS Rella Mareta, Ardianto Satriawan, Hanho Lee
2025	C	`conf`	Base Conversion RNS using Hybrid Barret-Karatsuba-Based Modulus Prime Cores for Homomorphic Multiplication. ISCAS Muhammad Ogin Hasanuddin, Rafael Aditya Cahyo W, Infall Syafalni, Nana Sutisna, Hanho Lee, Trio Adiono
2025	C	`conf`	Exploring Possibilities of BFV-based Homomorphic Encryption for Privacy-Preserving Image Processing. ISCAS Ardianto Satriawan, Rella Mareta, Hanho Lee
2025	J	`jnl`	High Throughput Arithmetic Computing Unit for BFV Homomorphic Encryption. IEEE Open J. Circuits Syst. Rella Mareta, Ardianto Satriawan, Hanho Lee
2025	J	`jnl`	High-Performance Unified Hardware Architecture for ML-DSA and ML-KEM PQC Standards. IEEE Access Quang Dang Truong, Yunseong Jang, Hanho Lee
2025	J	`jnl`	Highly-Efficient Hardware Architecture for ML-KEM PQC Standard. IEEE Open J. Circuits Syst. Haesung Jung, Quang Dang Truong, Hanho Lee
2025	J	`jnl`	Homomorphic Evaluation Cluster Architecture for Fully Homomorphic Encryption. IEEE Open J. Circuits Syst. Hanyoung Lee, Ardianto Satriawan, Hanho Lee
2025	J	`jnl`	Hybrid Number Theoretic Transform Architecture for Homomorphic Encryption. IEEE Trans. Very Large Scale Integr. Syst. Quang Dang Truong, Phap Duong-Ngoc, Hanho Lee
2025	C	`conf`	Secure and Reliable 6G Communications with BCH-Based GLDPC and Kyber. ICCE Linh Nguyen, Cheol-Hong Min, Hanho Lee, Tuy Tan Nguyen
2024	J	`jnl`	A Bootstrapping-Capable Configurable NTT Architecture for Fully Homomorphic Encryption. IEEE Access Rella Mareta, Ardianto Satriawan, Phap Duong-Ngoc, Hanho Lee
2024	J	`jnl`	A Configurable ML-KEM/Kyber Key-Encapsulation Hardware Accelerator Architecture. IEEE Trans. Circuits Syst. II Express Briefs Hyunseon Kim, Haesung Jung, Ardianto Satriawan, Hanho Lee
2024	—	`conf`	Automorphism Architecture for Bootstrapping Homomorphic Encryption. ISOCC Hanyoung Lee, Hanho Lee
2024	C	`conf`	Compact 2 ISCAS Rella Mareta, Hanho Lee
2024	J	`jnl`	Configurable Arithmetic Core Architecture for RNS-CKKS Homomorphic Encryption. IEEE Access Chulwoo Lee, Hanyoung Lee, Ardianto Satriawan, Hanho Lee
2024	J	`jnl`	Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard. IEEE Access Quang Dang Truong, Phap Duong-Ngoc, Hanho Lee
2024	—	`conf`	Efficient Polynomial Arithmetic and Hash Modules for ML-DSA and ML-KEM Standards. APCCAS Quang Dang Truong, Hanho Lee
2024	J	`jnl`	Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief. IEEE Trans. Circuits Syst. II Express Briefs Jiafeng Xie, Wenfeng Zhao, Hanho Lee, Debapriya Basu Roy, Xinmiao Zhang
2024	J	`jnl`	Integer Modular Multiplication With Barrett Reduction and Its Variants for Homomorphic Encryption Applications: A Comprehensive Review and an Empirical Study. IEEE Access Ardianto Satriawan, Rella Mareta, Hanho Lee
2023	J	`jnl`	An Efficient Unified Polynomial Arithmetic Unit for CRYSTALS-Dilithium. IEEE Trans. Circuits Syst. I Regul. Pap. Thang Xuan Pham, Phap Duong-Ngoc, Hanho Lee
2023	J	`jnl`	Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption. IEEE Trans. Circuits Syst. I Regul. Pap. Phap Duong-Ngoc, Sunmin Kwon, Donghoon Yoo, Hanho Lee
2023	C	`conf`	CKKS-Based Homomorphic Encryption Architecture using Parallel NTT Multiplier. ISCAS Tuy Tan Nguyen, Jisu Kim, Hanho Lee
2023	J	`jnl`	Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption. Sensors Jaehyeok Lee, Phap Duong-Ngoc, Hanho Lee
2023	J	`jnl`	Configurable Memory-Based NTT Architecture for Homomorphic Encryption. IEEE Trans. Circuits Syst. II Express Briefs Stefanus Kurniawan, Phap Duong-Ngoc, Hanho Lee
2023	J	`jnl`	Hamming-Distance Trellis Min-Max-Based Architecture for Non-Binary LDPC Decoder. IEEE Trans. Circuits Syst. II Express Briefs Thang Xuan Pham, Tuy Tan Nguyen, Hanho Lee
2023	J	`jnl`	Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption. Sensors Phap Duong-Ngoc, Hanho Lee
2023	—	`conf`	Twiddle Factor Generator Architecture for Number Theoretic Transform. ISOCC Chulwoo Lee, Hanyoung Lee, Phap Duong-Ngoc, Hanho Lee
2022	J	`jnl`	Configurable Mixed-Radix Number Theoretic Transform Architecture for Lattice-Based Cryptography. IEEE Access Phap Duong-Ngoc, Hanho Lee
2022	J	`jnl`	Efficient First Four Minimum Values Finder for NB-LDPC Decoders With Compressed Messages. IEEE Trans. Circuits Syst. II Express Briefs Thang Xuan Pham, Hanho Lee
2022	—	`conf`	Flexible GPU-Based Implementation of Number Theoretic Transform for Homomorphic Encryption. ISOCC Phap Duong-Ngoc, Thang Xuan Pham, Hanho Lee, Tuy Tan Nguyen
2022	—	`conf`	Low-Complexity Architecture of Finding First Four Minimum Values for Non-binary LDPC Decoders. ISOCC Thang Xuan Pham, Phap Duong-Ngoc, Hanho Lee, Tuy Tan Nguyen
2022	J	`jnl`	Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders. Sensors Tuy Tan Nguyen, Tram Thi Bao Nguyen, Hanho Lee
2022	—	`conf`	Toward A Real-Time Elliptic Curve Cryptography-Based Facial Security System. APCCAS Tuy Tan Nguyen, Hanho Lee
2021	—	`conf`	Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic Encryption. ISOCC Phap Duong-Ngoc, Tuy Nguyen Tan, Hanho Lee
2021	C	`conf`	High-Efficient Nonbinary LDPC Decoder with Early Layer Decoding Schedule. ISCAS Thang Xuan Pham, Hanho Lee
2021	J	`jnl`	Minimal-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Thang Xuan Pham, Tuy Nguyen Tan, Hanho Lee
2021	—	`conf`	Novel Performance Evaluation Approach of AMBA AXI-Based SoC Design. ISOCC Tuy Nguyen Tan, Phap Duong-Ngoc, Thang Xuan Pham, Hanho Lee
2020	—	`conf`	Efficient $k$-Parallel Pipelined NTT Architecture for Post Quantum Cryptography. ISOCC Phap Duong-Ngoc, Yong-Jin Kim, Hanho Lee
2020	—	`conf`	Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes. ISOCC Thang Xuan Pham, Hanho Lee
2020	J	`jnl`	Efficient NewHope Cryptography Based Facial Security System on a GPU. IEEE Access Phap Duong-Ngoc, Tuy Nguyen Tan, Hanho Lee
2019	J	`jnl`	Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes. Integr. Huyen Pham Thi, Hanho Lee, Xuan Nghia Pham
2019	J	`jnl`	High-Secure Fingerprint Authentication System Using Ring-LWE Cryptography. IEEE Access Tuy Nguyen Tan, Hanho Lee
2019	J	`jnl`	Low-complexity multi-mode multi-way split-row layered LDPC decoder for gigabit wireless communications. Integr. Tram Thi Bao Nguyen, Hanho Lee
2019	—	`conf`	Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder. APCCAS Huyen Pham Thi, Cuong Dinh The, Xuan Nghia Pham, Hung Dao Tuan, Hanho Lee
2018	J	`jnl`	Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields. IEEE Trans. Very Large Scale Integr. Syst. Huyen Thi Pham, Hanho Lee
2018	—	`conf`	Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture. ISOCC Tram Thi Bao Nguyen, Hanho Lee
2018	C	`conf`	High-Secure Low-Latency Ring-LWE Cryptography Scheme for Biomedical Images Storing and Transmitting. ISCAS Tuy Nguyen Tan, Hanho Lee
2018	Misc	`conf`	Reduced-Complexity Trellis Min-Max Decoder for Non-Binary Ldpc Codes. ICASSP Huyen Pham Thi, Hanho Lee
2017	C	`conf`	A delay-efficient ring-LWE cryptography architecture for biometric security. ISCAS Tuy Nguyen Tan, Hanho Lee
2017	J	`jnl`	High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes. Integr. Huyen Thi Pham, Sabooh Ajaz, Hanho Lee
2017	—	`conf`	Parallel architecture for concatenated polar-CRC codes. ISOCC Seunghun Oh, Hanho Lee
2017	J	`jnl`	Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. Huyen Thi Pham, Hanho Lee
2016	—	`conf`	Low latency check node unit architecture for nonbinary LDPC decoding. APCCAS Huyen Thi Pham, Hanho Lee
2015	J	`jnl`	Block-Layered Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes. J. Signal Process. Syst. Chang-Seok Choi, Hanho Lee
2015	J	`jnl`	Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications. Integr. Sabooh Ajaz, Hanho Lee
2015	—	`conf`	Parallel block-layered nonbinary QC-LDPC decoding on GPU. SiPS Huyen Thi Pham, Sabooh Ajaz, Hanho Lee
2014	J	`jnl`	An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders. IEICE Electron. Express Sabooh Ajaz, Hanho Lee
2014	—	`conf`	Multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad standard. APCCAS Sabooh Ajaz, Hanho Lee
2013	J	`jnl`	A High-Speed Low-Complexity Modified IEEE Trans. Very Large Scale Integr. Syst. Taesang Cho, Hanho Lee
2013	J	`jnl`	Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design. IEEE Trans. Very Large Scale Integr. Syst. Seong-In Hwang, Hanho Lee
2013	C	`conf`	High-performance iterative BCH decoder architecture for 100 Gb/s optical communications. ISCAS Jewong Yeon, Hanho Lee
2012	J	`jnl`	A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications. J. Signal Process. Syst. Kihoon Lee, Han-Gil Kang, Jeong-In Park, Hanho Lee
2012	J	`jnl`	A High-Speed Low-Complexity Time-Multiplexing Reed-Solomon-Based FEC Architecture for Optical Communications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jeong-In Park, Hanho Lee
2012	C	`conf`	A novel method of constructing Quasi-Cyclic RS-LDPC codes for 10GBASE-T Ethernet. ISCAS Seong-In Hwang, Hanho Lee, Shin-Il Lim
2012	—	`conf`	An ultra high-speed time-multiplexing Reed-Solomon-based FEC architecture. ISOCC Jeong-In Park, Jewong Yeon, Seung-Jun Yang, Hanho Lee
2012	—	`conf`	Biochemical sensor interface circuits with differential difference amplifier. APCCAS Shin-Il Lim, In-Sub Choi, Hanho Lee
2012	C	`conf`	Concatenated non-binary LDPC and HD-FEC codes for 100Gb/s optical transport systems. ISCAS Chang-Seok Choi, Hanho Lee, Noriaki Kaneda, Young-Kai Chen
2012	J	`jnl`	Implementations of Signal-Processing Algorithms for OFDM Systems. J. Electr. Comput. Eng. Ming-Der Shieh, Yin-Tsung Hwang, Hanho Lee, Chirn Chye Boon, Zhiyuan Yan
2011	J	`jnl`	A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes. IEEE Trans. Very Large Scale Integr. Syst. Sangmin Kim, Gerald E. Sobelman, Hanho Lee
2011	C	`conf`	A high-speed low-complexity modified radix-2 ISCAS Taesang Cho, Hanho Lee, Jounsup Park, Chulgyun Park
2011	C	`conf`	A high-throughput LDPC decoder architecture for high-rate WPAN systems. ISCAS Kyung-Il Baek, Hanho Lee, Chang-Seok Choi, Sangmin Kim, Gerald E. Sobelman
2011	C	`conf`	An area-efficient truncated inversionless Berlekamp-Massey architecture for Reed-Solomon decoders. ISCAS Jeong-In Park, Hanho Lee, Seongsoo Lee
2011	J	`jnl`	High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems. IEICE Trans. Commun. Chang-Seok Choi, Hyo-Jin Ahn, Hanho Lee
2011	J	`jnl`	Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yong-Kyu Kim, Chang-Seok Choi, Hanho Lee
2011	J	`jnl`	Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kisun Jung, Hanho Lee
2011	—	`conf`	Low-complexity filter and interpolator design for ATSC DTV systems. ISOCC Yong-Kyu Kim, Chang-Seok Choi, Hanho Lee, Jin-Gyun Chung
2010	J	`jnl`	High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sangho Yoon, Hanho Lee, Kihoon Lee
2010	—	`conf`	Low-cost variable-length FFT processor for DVB-T/H applications. APCCAS Kisun Jung, Hanho Lee
2009	—	`conf`	High-speed low-complexity three-parallel reed-solomon decoder for 6-Gbps mmWave WPAN systems. ECCTD Chang-Seok Choi, Hanho Lee
2009	—	`conf`	Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communications. SiPS Sangho Yoon, Hanho Lee, Kihoon Lee, Chang-Seok Choi, Jongyoon Shin, Jongho Kim, Je-Soo Ko
2008	—	`conf`	40-Gb/s two-parallel Reed-Solomon based Forward Error Correction architecture for optical communications. APCCAS Seungbeom Lee, Hanho Lee, Chang-Seok Choi, Jongyoon Shin, Je-Soo Ko
2008	—	`conf`	A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders. SoCC Sangho Yoon, Hanho Lee
2008	J	`jnl`	A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Seungbeom Lee, Hanho Lee
2008	J	`jnl`	A High-Speed Two-Parallel Radix-2 IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jeesung Lee, Hanho Lee
2008	—	`conf`	A high performance four-parallel 128/64-point radix-2 APCCAS Hang Liu, Hanho Lee
2008	C	`conf`	A high-speed four-parallel radix-2 ISCAS Minhyeok Shin, Hanho Lee
2008	C	`conf`	Adaptive quantization in min-sum based irregular LDPC decoder. ISCAS Sangmin Kim, Gerald E. Sobelman, Hanho Lee
2008	—	`conf`	Flexible LDPC decoder architecture for high-throughput applications. APCCAS Sangmin Kim, Gerald E. Sobelman, Hanho Lee
2008	C	`conf`	Two bit-level pipelined viterbi decoder for high-performance UWB applications. ISCAS Yong-Je Goo, Hanho Lee
2008	J	`jnl`	Two-parallel Reed-Solomon based FEC architecture for optical communications. IEICE Electron. Express Seungbeom Lee, Chang-Seok Choi, Hanho Lee
2007	J	`jnl`	A Design and Performance of 4-Parallel MB-OFDM UWB Receiver. IEICE Trans. Commun. Cheol-Ho Shin, Sangsung Choi, Hanho Lee, Jeong-Ki Pack
2007	C	`conf`	A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders. ISCAS Seungbeom Lee, Hanho Lee, Jongyoon Shin, Je-Soo Ko
2007	—	`conf`	A Partial Self-Reconfigurable Adaptive FIR Filter System. SiPS Chang-Seok Choi, Hanho Lee
2007	J	`jnl`	A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform. IEICE Trans. Inf. Syst. Chang-Seok Choi, Hanho Lee
2007	—	`conf`	Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications. ARC Yong-Min Lee, Chang-Seok Choi, Seung-Gon Hwang, Hyun Dong Kim, Chul Hong Min, Jaehyun Park, Hanho Lee, Tae-Seon Kim, Chong Ho Lee
2006	C	`conf`	A high-speed, low-complexity radix-2 ISCAS Jeesung Lee, Hanho Lee, Sang-In Cho, Sangsung Choi
2006	C	`conf`	A reconfigurable FIR filter design using dynamic partial reconfiguration. ISCAS Yeong-Jae Oh, Hanho Lee, Chong Ho Lee
2006	—	`conf`	Dynamic Partial Reconfigurable FIR Filter Design. ARC Yeong-Jae Oh, Hanho Lee, Chong Ho Lee
2006	—	`conf`	Implementation of a FIR Filter on a Partial Reconfigurable Platform. KES (3) Hanho Lee, Chang-Seok Choi
2005	J	`jnl`	A high-speed low-complexity Reed-Solomon decoder for optical communications. IEEE Trans. Circuits Syst. II Express Briefs Hanho Lee
2005	—	`conf`	An Evolvable Hardware System Under Uneven Environment. KES (2) In Ja Jeon, Phill-Kyu Rhee, Hanho Lee
2005	—	`conf`	An ultra high-speed Reed-Solomon decoder. ISCAS (2) Hanho Lee
2005	J	`jnl`	Power-Aware Scalable Pipelined Booth Multiplier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hanho Lee
2005	—	`conf`	Reconfigurable Power-Aware Scalable Booth Multiplier. KES (1) Hanho Lee
2004	—	`conf`	A power-aware scalable pipelined Booth multiplier. SoCC Hanho Lee
2004	J	`jnl`	VLSI Design Of Digit-Serial FPGA Architecture. J. Circuits Syst. Comput. Hanho Lee, Gerald E. Sobelman
2003	—	`conf`	An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder. ISVLSI Hanho Lee
2003	—	`conf`	High-speed VLSI architecture for parallel Reed-Solomon decoder. ISCAS (2) Hanho Lee
2003	J	`jnl`	High-speed VLSI architecture for parallel Reed-Solomon decoder. IEEE Trans. Very Large Scale Integr. Syst. Hanho Lee
2003	J	`jnl`	Performance evaluation and optimal design for FPGA-based digit-serial DSP functions. Comput. Electr. Eng. Hanho Lee, Gerald E. Sobelman
2000	C	`conf`	VLSI design of Reed-Solomon decoder architectures. ISCAS Hanho Lee, Meng-Lin Yu, Leilei Song
1999	Misc	`conf`	A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor. FCCM Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman
1998	Misc	`conf`	Digit-Serial DSP Library for Optimized FPGA Configuration. FCCM Hanho Lee, Gerald E. Sobelman
1998	A	`conf`	FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract). FPGA Hanho Lee, Sarvesh Shrivastava, Gerald E. Sobelman
1997	—	`conf`	A New Low-Voltage Full Adder Circuit. Great Lakes Symposium on VLSI Hanho Lee, Gerald E. Sobelman