Han-Gon Ko - RankMe

33 papers C 1Journal 18Unranked 14

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	37.9 A 14Gb/s/pin 0.163pJ/b DQ Receiver for HBM with Baud-Rate Phase Tracking Loop Supporting Background Offset Calibration. ISSCC Jeonghyeon Lee, Ho-Joon Shin, Han-Gon Ko, Kwanseo Park
2025	J	`jnl`	An 18-Tb/s/mm PAM-3 On-Chip Link With Jitter-Suppressing 3T4T Coding and FFE-Based Crosstalk Cancellation for Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. Dongwoo Kang, Jun-Soo Park, Young-Wook Kim, Sinho Lee, Kyugun Kim, Han-Gon Ko, Kwanseo Park
2024	J	`jnl`	A 3×12 -Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Dongwoo Kang, Han-Gon Ko, Kwanseo Park
2023	—	`conf`	A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS. ISSCC Jung-Hun Park, Hyeonseok Lee, Hoyeon Cho, Sanghee Lee, Kwang-Hoon Lee, Han-Gon Ko, Deog-Kyoon Jeong
2022	—	`conf`	A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. ESSCIRC Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong
2022	J	`jnl`	A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO. IEEE Trans. Circuits Syst. II Express Briefs Yeonggeun Song, Han-Gon Ko, Changhyun Kim, Deog-Kyoon Jeong
2022	—	`conf`	A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller. VLSI Technology and Circuits Jung-Hun Park, Kwang-Hoon Lee, Yongjae Lee, Jung-Woo Sull, Yoonho Song, Sanghee Lee, Hyeonseok Lee, Hoyeon Cho, Jonghyun Oh, Han-Gon Ko, Deog-Kyoon Jeong
2022	J	`jnl`	Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector. IEEE J. Solid State Circuits Kwanseo Park, Minkyo Shim, Han-Gon Ko, Borivoje Nikolic, Deog-Kyoon Jeong
2021	—	`conf`	0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link. ESSCIRC Woonghee Lee, Minkyo Shim, Yunhee Lee, Heejin Yang, Han-Gon Ko, Woo-Seok Choi, Deog-Kyoon Jeong
2021	J	`jnl`	0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop. IEEE Trans. Circuits Syst. II Express Briefs Chang-Soo Yoon, Han-Gon Ko, Byung-Jun Kang, Jung-Woo Sull, Deog-Kyoon Jeong
2021	J	`jnl`	A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. IEEE Access Byungjun Kang, Gyu-Seob Jeong, Jeongho Hwang, Kwanseo Park, Hyungrok Do, Hyojun Kim, Han-Gon Ko, Moon-Chul Choi, Deog-Kyoon Jeong
2021	J	`jnl`	A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong
2020	—	`conf`	22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface. ISSCC Soyeong Shin, Han-Gon Ko, Sungchun Jang, Dongkyun Kim, Deog-Kyoon Jeong
2020	—	`conf`	6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS. ISSCC Kwanseo Park, Minkyo Shim, Han-Gon Ko, Deog-Kyoon Jeong
2020	—	`conf`	6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels. ISSCC Han-Gon Ko, Soyeong Shin, Jonghyun Oh, Kwanseo Park, Deog-Kyoon Jeong
2020	—	`conf`	A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler. VLSI Circuits Moon-Chul Choi, Han-Gon Ko, Jonghyun Oh, Hye-Yoon Joo, Kwangho Lee, Deog-Kyoon Jeong
2020	J	`jnl`	A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs Soyeong Shin, Han-Gon Ko, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Doobock Lee, Hae-Kang Jung, Suhwan Kim, Deog-Kyoon Jeong
2020	J	`jnl`	A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. IEEE Trans. Circuits Syst. II Express Briefs Sangyoon Lee, Han-Gon Ko, Joo-Hyung Chae, Soyeong Shin, Jaekwang Yun, Deog-Kyoon Jeong, Suhwan Kim
2020	J	`jnl`	A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Chan-Ho Kye, Han-Gon Ko, Jinhyung Lee, Deog-Kyoon Jeong
2020	J	`jnl`	A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation. IEEE Trans. Very Large Scale Integr. Syst. Hye-Yoon Joo, Jinhyung Lee, Haram Ju, Han-Gon Ko, Jungmin Yoon, Byungjun Kang, Deog-Kyoon Jeong
2019	J	`jnl`	A 10-Gb/s, 0.03-mm IEEE J. Solid State Circuits Min-Seong Choo, Kwanseo Park, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2019	J	`jnl`	A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Trans. Circuits Syst. II Express Briefs Min-Seong Choo, Yeonggeun Song, Sung-Yong Cho, Han-Gon Ko, Kwanseo Park, Deog-Kyoon Jeong
2019	J	`jnl`	A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. IEEE Trans. Circuits Syst. II Express Briefs Moon-Chul Choi, Deog-Kyoon Jeong, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko, Haram Ju, Kwanseo Park, Hyojun Kim, Kwandong Kim
2019	—	`conf`	A 370-fJ/b, 0.0056 mm VLSI Circuits Han-Gon Ko, Soyeong Shin, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Hae-Kang Jung, Doobock Lee, Suhwan Kim, Deog-Kyoon Jeong
2019	—	`conf`	A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS. ICEIC Moon-Chul Choi, Haram Ju, Han-Gon Ko, Deog-Kyoon Jeong
2019	J	`jnl`	Reference Spur Reduction Techniques for a Phase-Locked Loop. IEEE Access Han-Gon Ko, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2018	J	`jnl`	25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Trans. Circuits Syst. II Express Briefs Gyu-Seob Jeong, Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han-Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2018	—	`conf`	A 10-Gb/s, 0.03-mm A-SSCC Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2018	J	`jnl`	A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. IEEE Trans. Circuits Syst. I Regul. Pap. Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong
2018	J	`jnl`	An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. IEEE Trans. Circuits Syst. II Express Briefs Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2017	—	`conf`	29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. ISSCC Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin, Min-Seong Choo, Hankyu Chi, Deog-Kyoon Jeong
2016	C	`conf`	A theoretical analysis of phase shift in pulse injection-locked oscillators. ISCAS Jinhyung Lee, Sungwoo Kim, Min-Seong Choo, Sung-Yong Cho, Han-Gon Ko, Deog-Kyoon Jeong
2015	—	`conf`	A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. ESSCIRC Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong