Hamid R. Zarandi

106 papers A 2B 5C 24Misc 3Journal 46Unranked 26

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A reliability framework for NB-IoT devices: Addressing transient faults and silent data corruptions. Comput. Electr. Eng. Fatemeh Khojasteh Dana, Seyedeh Fatemeh Anvari, Hamid R. Zarandi
2025	J	`jnl`	An Empirical Fault Vulnerability Exploration of ReRAM-Based Process-in-Memory CNN Accelerators. IEEE Trans. Reliab. Aniseh Dorostkar, Hamed Farbeh, Hamid R. Zarandi
2025	J	`jnl`	OptGM: An Optimized Gate Merging Method to Mitigate NBTI in Digital Circuits. CoRR Maryam Ghane, Amir M. Hajisadeghi, Hamid R. Zarandi
2025	Misc	`conf`	Optimizing Proof-of-Work Blockchain Network Communications Using Genetic Algorithm. CSICC Arman Gheysari, Murtadha Almahdawi, Hamid R. Zarandi
2025	J	`jnl`	Security-aware optimization of PoW-based blockchain performance using a genetic algorithm approach. Sustain. Comput. Informatics Syst. Arman Gheysari, Hamid R. Zarandi
2025	J	`jnl`	Simultaneous optimization of network-on-chip to improve reliability and reduce average packet latency considering buffer size constraints. J. Supercomput. Hesam Abdolhosseini, Hamid R. Zarandi, Arman Gheysari
2024	J	`jnl`	Approx-IMC: A general-purpose approximate digital in-memory computing framework based on STT-MRAM. Future Gener. Comput. Syst. Amir M. Hajisadeghi, Mahmoud Momtazpour, Hamid R. Zarandi
2024	J	`jnl`	Online Soft Error Tolerance in ReRAM Crossbars for Deep Learning Accelerators. CoRR Benyamin Khezeli, Hamid R. Zarandi, Elham Cheshmikhani
2024	J	`jnl`	Stoch-IMC: A Bit-Parallel Stochastic In-Memory Computing Architecture Based on STT-MRAM. CoRR Amir M. Hajisadeghi, Hamid R. Zarandi, Mahmoud Momtazpour
2022	C	`conf`	EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis. DSD Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi
2022	Misc	`conf`	ThingsDND: IoT Device Failure Detection and Diagnosis for Multi-User Smart Homes. EDCC Alireza Borhani, Hamid R. Zarandi
2021	J	`jnl`	A High Performance, Multi-Bit Output Logic-in-Memory Adder. IEEE Trans. Emerg. Top. Comput. Javad Talafy, Farzaneh Zokaee, Hamid R. Zarandi, Nader Bagherzadeh
2021	J	`jnl`	CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics. Microprocess. Microsystems Amir M. Hajisadeghi, Hamid R. Zarandi
2020	J	`jnl`	DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories. Microprocess. Microsystems Saeed Seyedfaraji, Amir M. Hajisadeghi, Javad Talafy, Hamid R. Zarandi
2020	J	`jnl`	IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes. Microprocess. Microsystems Alireza Tajary, Hamid R. Zarandi, Nader Bagherzadeh
2019	Misc	`conf`	A Fast and Efficient Fault Tree Analysis Using Approximate Computing. EDCC Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi, Saadat Pour-Mozafari
2019	J	`jnl`	A meta heuristic-based task scheduling and mapping method to optimize main design challenges of heterogeneous multiprocessor embedded systems. Microelectron. J. Athena Abdi, Hamid R. Zarandi
2019	J	`jnl`	ERPOT: A Quad-Criteria Scheduling Heuristic to Optimize Execution Time, Reliability, Power Consumption and Temperature in Multicores. IEEE Trans. Parallel Distributed Syst. Athena Abdi, Alain Girault, Hamid R. Zarandi
2019	J	`jnl`	Lifetime Reliability Enhancement in Multiprocessor Systems Through a Fine-Grained System-Level Approach. J. Circuits Syst. Comput. Athena Abdi, Masoomeh Karami, Hamid R. Zarandi
2018	C	`conf`	A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays. IOLTS Hossein Bardareh, Amir M. Hajisadeghi, Hamid R. Zarandi
2018	J	`jnl`	A cross-layer aging-aware task scheduling approach for multiprocessor embedded systems. Microelectron. Reliab. Masoomeh Karami, Athena Abdi, Hamid R. Zarandi
2018	J	`jnl`	AligneR: A Process-in-Memory Architecture for Short Read Alignment in ReRAMs. IEEE Comput. Archit. Lett. Farzaneh Zokaee, Hamid R. Zarandi, Lei Jiang
2018	C	`conf`	DUSTER: DUal Source Write TERmination Method for STT-RAM Memories. DSD Saaed S. Faraji, Javad Talafy, Amir M. Hajisadeghi, Hamid R. Zarandi
2018	J	`jnl`	HYSTERY: a hybrid scheduling and mapping approach to optimize temperature, energy consumption and lifetime reliability of heterogeneous multiprocessor systems. J. Supercomput. Athena Abdi, Hamid R. Zarandi
2018	C	`conf`	MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational Circuits. DSD Amir M. Hajisadeghi, Hossein Bardareh, Hamid R. Zarandi
2017	—	`conf`	Context-Aware Anomaly Detection in Embedded Systems. DepCoS-RELCOMEX Fatemeh Ehsani-Besheli, Hamid R. Zarandi
2017	—	`conf`	Designing a differential 3R-2bit RRAM cell for enhancing read margin in cross-point RRAM arrays. NORCAS Mohammadreza Nakhkash, Hossein Bardareh, Farzaneh Zokaee, Hamid R. Zarandi
2017	J	`jnl`	Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on Field-Programmable Gate Arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk. Qual. Reliab. Eng. Int. Shahab Shoar, Hamid R. Zarandi, Farnad Nasirzadeh, Elham Cheshmikhani
2017	C	`conf`	Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution. IOLTS Javad Talafy, Hamid R. Zarandi
2016	C	`conf`	A Cluster-Based Method to Detect and Correct Anomalies in Sensor Data of Embedded Systems. PDP Roghayeh Mojarad, Hossain Kordestani, Hamid R. Zarandi
2016	C	`conf`	Accelerating Dynamic Fault Tree Analysis Based on Stochastic Logic Utilizing GPGPUs. PDP Elham Cheshmikhani, Hamid R. Zarandi
2016	C	`conf`	An Efficient Soft Error Detection in Multicore Processors Running Server Applications. PDP Alireza Tajary, Hamid R. Zarandi
2016	J	`jnl`	Double Stairs: A Fault-Tolerant Routing Algorithm for Networks-on-Chip. J. Circuits Syst. Comput. Saleh Fakhrali, Hamid R. Zarandi
2016	C	`conf`	Gate Merging: An NBTI Mitigation Method to Eliminate Critical Internal Nodes in Digital Circuits. PDP Maryam Ghane, Hamid R. Zarandi
2016	J	`jnl`	Leveraging the Potential of Control-Flow Error Resilient Techniques in Multithreaded Programs. CoRR Navid Khoshavi, Mohammad Maghsoudloo, Hamid R. Zarandi
2016	C	`conf`	MWPF: A Deadlock Avoidance Fully Adaptive Routing Algorithm in Networks-on-Chip. PDP Kamran Nasiri, Hamid R. Zarandi
2016	—	`conf`	Postponing wearout failures in chip multiprocessors using thermal management and thread migration. ReCoSoC Elham Kashefi, Hamid R. Zarandi, Ann Gordon-Ross
2016	J	`jnl`	Using instruction result locality and re-execution to mitigate silent data corruptions. Microelectron. Reliab. Alireza Tajary, Hamid R. Zarandi
2015	J	`jnl`	Design space exploration of non-uniform cache access for soft-error vulnerability mitigation. Microelectron. Reliab. Mohammad Maghsoudloo, Hamid R. Zarandi
2015	J	`jnl`	Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates. Microelectron. Reliab. Elham Cheshmikhani, Hamid R. Zarandi
2014	J	`jnl`	Cache vulnerability mitigation using an adaptive cache coherence protocol. J. Supercomput. Mohammad Maghsoudloo, Hamid R. Zarandi
2014	J	`jnl`	DFTS: A dynamic fault-tolerant scheduling for real-time tasks in multicore processors. Microprocess. Microsystems Mohammad Hadi Mottaghi, Hamid R. Zarandi
2014	J	`jnl`	Fxy: a Hierarchical Routing Algorithm to Balance Performance and Fault Tolerance in Networks-on-Chip. J. Circuits Syst. Comput. Saleh Fakhrali, Hamid R. Zarandi
2014	J	`jnl`	Reliability improvement in private non-uniform cache architecture using two enhanced structures for coherence protocols and replacement policies. Microprocess. Microsystems Mohammad Maghsoudloo, Hamid R. Zarandi
2013	J	`jnl`	A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays. IEEE Trans. Reliab. Hananeh Aliee, Hamid R. Zarandi
2013	C	`conf`	A Reliability-Aware Multi-application Mapping Technique in Networks-on-Chip. PDP Fatemeh Khalili, Hamid R. Zarandi
2013	J	`jnl`	A fault-tolerant core mapping technique in networks-on-chip. IET Comput. Digit. Tech. Fatemeh Khalili, Hamid R. Zarandi
2013	J	`jnl`	A parallel clustering algorithm on the star graph and its performance. Math. Comput. Model. Hamid Sarbazi-Azad, Hamid R. Zarandi, Mahdi Fazeli
2012	—	`conf`	A Fault-Tolerant Low-Energy Multi-Application Mapping onto NoC-based Multiprocessors. CSE Fatemeh Khalili, Hamid R. Zarandi
2012	—	`conf`	A fault-aware low-energy spare core allocation in networks-on-chip. NORCHIP Fatemeh Khalili, Hamid R. Zarandi
2012	J	`jnl`	An efficient adaptive software-implemented technique to detect control-flow errors in multi-core architectures. Microelectron. Reliab. Mohammad Maghsoudloo, Hamid R. Zarandi, Navid Khoshavi
2012	—	`conf`	Dirty data vulnerability mitigation by means of sharing management in cache coherence protocols. DFT Mohammad Maghsoudloo, Hamid R. Zarandi
2012	—	`conf`	Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets. CSE Hamed Abbasitabar, Hamid R. Zarandi, Ronak Salamat
2012	J	`jnl`	Two effective methods to detect anomalies in embedded systems. Microelectron. J. Mahroo Zandrahimi, Hamid R. Zarandi, Mohammad Hadi Mottaghi
2011	B	`conf`	A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for Chip Multiprocessors. SAFECOMP Hananeh Aliee, Hamid R. Zarandi
2011	J	`jnl`	An adaptive method to tolerate soft errors in SRAM-based FPGAs. Sci. Iran. Somayeh Bahramnejad, Hamid R. Zarandi
2011	—	`conf`	An efficient, dynamically adaptive method to tolerate transient faults in multi-core systems. EWDC Hananeh Aliee, Hamid R. Zarandi
2011	—	`conf`	CPU-aware, process-level redundancy to tolerate faults in multi-core. HPCS Hananeh Aliee, Hamid R. Zarandi, Alireza Tajary
2011	—	`conf`	Control-flow error detection using combining basic and program-level checking in commodity multi-core architectures. SIES Navid Khoshavi, Hamid R. Zarandi, Mohammad Maghsoudloo
2011	C	`conf`	Control-flow error recovery using commodity multi-core architecture features. IOLTS Navid Khoshavi, Hamid R. Zarandi, Mohammad Maghsoudloo
2011	C	`conf`	Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire. IOLTS Ronak Salamat, Hamid R. Zarandi
2011	J	`jnl`	HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors. Des. Autom. Embed. Syst. Mostafa Kishani, Hamid R. Zarandi, Hossein Pedram, Alireza Tajary, Mohsen Raji, Behnam Ghavami
2011	J	`jnl`	Investigation of transient fault effects in synchronous and asynchronous Network on Chip router. J. Syst. Archit. Pooria M. Yaghini, Ashkan Eghbal, Hossein Pedram, Hamid R. Zarandi
2011	—	`conf`	Low-Cost Software-Implemented Error Detection Technique. ISED Mohammad Maghsoudloo, Hamid R. Zarandi, Navid Khoshavi
2011	J	`jnl`	Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes. Microelectron. J. Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi
2011	J	`jnl`	Mitigation of soft errors in SRAM-based FPGAs using CAD tools. Comput. Electr. Eng. Somayeh Bahramnejad, Hamid R. Zarandi
2011	C	`conf`	Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring. DSD Mohammad Maghsoudloo, Hamid R. Zarandi, Saadat Pour-Mozafari, Navid Khoshavi
2010	—	`conf`	A Probabilistic Method to Detect Anomalies in Embedded Systems. DFT Mahroo Zandrahimi, Alireza Zarei, Hamid R. Zarandi
2010	—	`conf`	A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs. ASP-DAC Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi
2010	B	`conf`	An Adaptive Redundancy Oriented Method to Tolerate Soft Errors in SRAM-Based FPGAs Using Unused Resources. ARES Somayeh Bahramnejad, Hamid R. Zarandi
2010	B	`conf`	Analysis of Transient Faults on a MIPS-Based Dual-Core Processor. ARES Iman Faraji, Moslem Didehban, Hamid R. Zarandi
2010	C	`conf`	Investigation of Transient Fault Effects in an Asynchronous NoC Router. PDP Pooria M. Yaghini, Ashkan Eghbal, Hossein Pedram, Hamid R. Zarandi
2010	J	`jnl`	Performance modeling of n-dimensional mesh networks. Perform. Evaluation Pedram Rajabzadeh, Hamid Sarbazi-Azad, Hamid R. Zarandi, Ebrahim Khodaie, Hashem Hashemi Najaf-abadi, Mohamed Ould-Khaoua
2010	J	`jnl`	Process variation-aware performance analysis of asynchronous circuits. Microelectron. J. Mohsen Raji, Behnam Ghavami, Hossein Pedram, Hamid R. Zarandi
2010	—	`conf`	Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations. PATMOS Mohsen Raji, Alireza Tajary, Behnam Ghavami, Hossein Pedram, Hamid R. Zarandi
2010	C	`conf`	Two Efficient Software Techniques to Detect and Correct Control-Flow Errors. PRDC Hamid R. Zarandi, Mohammad Maghsoudloo, Navid Khoshavi
2010	J	`jnl`	Two effective methods to mitigate soft error effects in SRAM-based FPGAs. Microelectron. Reliab. Alireza Rohani, Hamid R. Zarandi
2009	—	`conf`	A Fault Injection Attitude based on Background Debug Mode in Embedded Systems. CDES Seyyed Amir Asghari, Hamid R. Zarandi, Hossein Pedram, Morteza Ansarinia, Mohammad Khademi
2009	—	`conf`	A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs. ReConFig Alireza Rohani, Hamid R. Zarandi
2009	B	`conf`	An Analysis of Fault Effects and Propagations in AVR Microcontroller ATmega103(L). ARES Alireza Rohani, Hamid R. Zarandi
2009	—	`conf`	Diagnosis of faults in template-based asynchronous circuits. SoC Behnam Ghavami, Hamid R. Zarandi, Arezoo Salarpour, Hossein Pedram
2009	C	`conf`	Fault injection-based evaluation of a synchronous NoC router. IOLTS Ashkan Eghbal, Pooria M. Yaghini, Hossein Pedram, Hamid R. Zarandi
2009	—	`conf`	Fault tolerance assessment of PIC microcontroller based on fault injection. LATW Ashkan Eghbal, Hamid R. Zarandi, Pooria M. Yaghini
2009	—	`conf`	Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation. PATMOS Mohsen Raji, Behnam Ghavami, Hamid R. Zarandi, Hossein Pedram
2007	J	`jnl`	A SEU-protected cache memory-based on variable associativity of sets. Reliab. Eng. Syst. Saf. Hamid R. Zarandi, Seyed Ghassem Miremadi
2007	C	`conf`	CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. ISCAS Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
2007	C	`conf`	CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. ISCAS Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
2007	J	`jnl`	Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs. Microelectron. Reliab. Hamid R. Zarandi, Seyed Ghassem Miremadi
2007	A	`conf`	Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. IPDPS Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
2007	—	`conf`	Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. DFT Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan
2007	C	`conf`	Multiple Upsets Tolerance in SRAM Memory. ISCAS Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan
2007	—	`conf`	SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. ISQED Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
2007	C	`conf`	Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. ISCAS Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
2006	J	`jnl`	A fault-tolerant cache architecture based on binary set partitioning. Microelectron. Reliab. Hamid R. Zarandi, Seyed Ghassem Miremadi
2006	J	`jnl`	Hierarchical Set-Associate Cache for High-Performance and Low-Energy Architecture. J. Circuits Syst. Comput. Hamid R. Zarandi, Seyed Ghassem Miremadi
2005	J	`jnl`	Hierarchical Binary Set Partitioning in Cache Memories. J. Supercomput. Hamid R. Zarandi, Hamid Sarbazi-Azad
2005	—	`conf`	Hierarchical Multiple Associative Mapping in Cache Memories. ECBS Hamid R. Zarandi, Seyed Ghassem Miremadi
2005	—	`conf`	Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme. LADC Hamid R. Zarandi, Seyed Ghassem Miremadi
2004	B	`conf`	A Highly Fault Detectable Cache Architecture for Dependable Computing. SAFECOMP Hamid R. Zarandi, Seyed Ghassem Miremadi
2004	—	`conf`	A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models. ESA/VLSI Hamid R. Zarandi, Seyed Ghassem Miremadi, Shaahin Hessabi, Ali Reza Ejlali
2004	C	`conf`	Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. PRDC Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali
2004	C	`conf`	Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm. IOLTS Hamid R. Zarandi, Seyed Ghassem Miremadi, Hamid Sarbazi-Azad
2003	A	`conf`	A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. DSN Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi
2003	—	`conf`	Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. DFT Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali
2003	C	`conf`	Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems. ISPDC Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali
2003	—	`conf`	Fault injection into SRAM-based FPGAs for the analysis of SEU effects. FPT Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Alireza Ejlali