Hamid Mahmoodi-Meimand

33 papers A* 1A 6C 2Misc 3Journal 9Unranked 12

Year	Rank	Type	Title / Venue / Authors
2006	J	`jnl`	A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. IEEE Trans. Very Large Scale Integr. Syst. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
2006	Misc	`conf`	Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
2006	A	`conf`	Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia
2006	—	`conf`	Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	A	`conf`	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
2005	—	`conf`	A high speed and leakage-tolerant domino logic for high fan-in gates. ACM Great Lakes Symposium on VLSI Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi
2005	A*	`conf`	A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	J	`jnl`	A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. Very Large Scale Integr. Syst. Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy
2005	—	`conf`	Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. ISQED Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	A	`conf`	Double-gate SOI devices for low-power and high-performance applications. ICCAD Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
2005	Misc	`conf`	Dual-Edge Triggered Static Pulsed Flip-Flops. VLSI Design Aliakbar Ghadiri, Hamid Mahmoodi-Meimand
2005	J	`jnl`	Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. Very Large Scale Integr. Syst. Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
2005	—	`conf`	Energy recovery clocked dynamic logic. ACM Great Lakes Symposium on VLSI Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy
2005	—	`conf`	Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	J	`jnl`	Low-power scan design using first-level supply gating. IEEE Trans. Very Large Scale Integr. Syst. Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy
2005	Misc	`conf`	Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
2005	J	`jnl`	Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	C	`conf`	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	—	`conf`	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy
2005	—	`conf`	Pre-capturing static pulsed flip-flops. ISCAS (3) Aliakbar Ghadiri, Hamid Mahmoodi-Meimand
2004	C	`conf`	A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy
2004	J	`jnl`	Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE J. Solid State Circuits Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Yongtao Wang, Hunsoo Choo, Kaushik Roy
2004	—	`conf`	Data-retention flip-flops for power-down applications. ISCAS (2) Hamid Mahmoodi-Meimand, Kaushik Roy
2004	J	`jnl`	Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style. IEEE Trans. Circuits Syst. I Regul. Pap. Hamid Mahmoodi-Meimand, Kaushik Roy
2004	—	`conf`	Dual-edge triggered level converting flip-flops. ISCAS (2) Hamid Mahmoodi-Meimand, Kaushik Roy
2004	—	`conf`	Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits. CICC Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Kaushik Roy
2004	—	`conf`	First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
2004	A	`conf`	Statistical design and optimization of SRAM cell for yield enhancement. ICCAD Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
2003	A	`conf`	Energy recovery clocking scheme and flip-flops for ultra low-energy applications. ISLPED Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy
2003	J	`jnl`	Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE Kauschick Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand
2002	A	`conf`	High performance and low power FIR filter design based on sharing multiplication. ISLPED Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy
2002	J	`jnl`	Leakage Current in Deep-Submicron CMOS Circuits. J. Circuits Syst. Comput. Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand
2001	—	`conf`	Efficient power clock generation for adiabatic logic. ISCAS (4) Hamid Mahmoodi-Meimand, Ali Afzali-Kusha