Hamed Fatemi

27 papers A* 1A 6B 1C 1Journal 10Unranked 8
YearRankTypeTitle / Venue / Authors
2020 J jnl
Heuristic Methods for Fine-Grain Exploitation of FDSOI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hamed Fatemi, Andrew B. Kahng, Hyein Lee, José Pineda de Gyvez
2020 — conf
Optimal bounded-skew steiner trees to minimize maximum
SLIP
Hamed Fatemi, Andrew B. Kahng, Minsoo Kim, José Pineda de Gyvez
2019 J jnl
Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs.
Integr.
P. Anagnostou, Andres Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini
2019 J jnl
Enhancing sensitivity-based power reduction for an industry IC design context.
Integr.
Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez
2019 C conf
Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network.
DSD
Emad A. Ibrahim, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez
2019 J jnl
Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention.
IEEE Trans. Very Large Scale Integr. Syst.
Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez
2018 J jnl
CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units.
IEEE Trans. Computers
Xun Jiao, Abbas Rahimi, Yu Jiang, Jianguo Wang, Hamed Fatemi, José Pineda de Gyvez, Rajesh K. Gupta
2018 — conf
Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths.
ACM Great Lakes Symposium on VLSI
Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez
2018 — conf
Low power latch based design with smart retiming.
ISQED
Kamlesh Singh, Hailong Jiao, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez
2018 — conf
Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs.
PATMOS
P. Anagnostou, Andres Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini
2017 J jnl
A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling.
IEEE J. Solid State Circuits
Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, Kofi A. A. Makinwa, José Pineda de Gyvez
2017 A conf
A scan-chain based state retention methodology for IoT processors operating on intermittent energy.
DATE
Pascal Alexander Hager, Hamed Fatemi, José Pineda de Gyvez, Luca Benini
2017 — conf
Floorplan and placement methodology for improved energy reduction in stacked power-domain design.
ASP-DAC
Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez
2017 J jnl
Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors.
Microprocess. Microsystems
Andres Gomez, Andrea Bartolini, Davide Rossi, Baris Can Kara, Hamed Fatemi, José Pineda de Gyvez, Luca Benini
2017 J jnl
Logic Design Partitioning for Stacked Power Domains.
IEEE Trans. Very Large Scale Integr. Syst.
Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, José Pineda de Gyvez
2016 — conf
A microcontroller with 96% power-conversion efficiency using stacked voltage domains.
VLSI Circuits
Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, José Pineda de Gyvez, Kofi A. A. Makinwa
2016 A conf
Circuit valorization in the IC design ecosystem.
ICCAD
José Pineda de Gyvez, Hamed Fatemi, Maarten Vertregt
2016 A* conf
Lower power by voltage stacking: a fine-grained system design approach.
DAC
Kristof Blutman, Ajay Kapoor, Jacinto Garcia Martinez, Hamed Fatemi, José Pineda de Gyvez
2015 A conf
Reducing energy consumption in microcontroller-based platforms with low design margin co-processors.
DATE
Andres Gomez, Christian Pinto, Andrea Bartolini, Davide Rossi, Luca Benini, Hamed Fatemi, José Pineda de Gyvez
2015 — conf
Supervised learning based model for predicting variability-induced timing errors.
NEWCAS
Xun Jiao, Abbas Rahimi, Balakrishnan Narayanaswamy, Hamed Fatemi, José Pineda de Gyvez, Rajesh K. Gupta
2014 J jnl
Digital Systems Power Management for High Performance Mixed Signal Platforms.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ajay Kapoor, Cas Groot, Gerard Villar Pique, Hamed Fatemi, Juan Diego Echeverri, Leo Sevat, Maarten Vertregt, Maurice Meijer, Vibhu Sharma, Yu Pu, José Pineda de Gyvez
2012 A conf
Sliding-Mode Control to Compensate PVT Variations in dual core systems.
DATE
Hamid Reza Pourshaghaghi, Hamed Fatemi, José Pineda de Gyvez
2008 A conf
DC-SIMD : Dynamic communication for SIMD processors.
IPDPS
Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Corporaal
2006 — conf
Dynamic-SIMD for lens distortion compensation.
ASAP
Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten
2006 J jnl
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications.
J. Embed. Comput.
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Richard P. Kleihorst
2006 A conf
Run-time reconfiguration of communication in SIMD architectures.
IPDPS
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Pieter P. Jonker
2005 B conf
Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures.
ACIVS
Hamed Fatemi, Henk Corporaal, Twan Basten, Richard P. Kleihorst, Pieter P. Jonker