Hajime Shibata

33 papers C 1Journal 15Unranked 17

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors. ISSCC Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Qingnan Yu, Zhao Li, Zeynep Lulec, Konstantinos Vasilakopoulos, Prawal Shrestha, Donald Paterson, Raviteja Theertham, Aseer Chowdhury
2024	J	`jnl`	A -90-dBFS-IM IEEE J. Solid State Circuits Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Prawal Shrestha, Zhao Li, Sevil Zeynep Lulec, Konstantinos Vasilakopoulos, Raviteja Theertham, Donald Paterson, Qingnan Yu, Aseer Chowdhury
2024	J	`jnl`	A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. IEEE J. Solid State Circuits Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
2023	—	`conf`	A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs. CICC Sharvil Patil, Raviteja Theertham, Hajime Shibata, Victor Kozlov, Asha Ganesan, Efram Burlingame, Zhao Li, Rama Thakar, Qianqian Zhang, Yue Yin, Aathreya S. Bhat
2023	—	`conf`	A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. VLSI Technology and Circuits Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
2022	J	`jnl`	A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Mohammed Wagih Ismail, Hajime Shibata, Zhao Li, Sharvil Patil, Tony Chan Carusone
2021	J	`jnl`	Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan, Hajime Shibata
2020	—	`conf`	16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. ISSCC Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya S. Bhat, Shanthi Pavan
2018	J	`jnl`	A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique. IEEE Trans. Circuits Syst. II Express Briefs Jialin Zhao, Yunzhi Dong, Wenhua Yang, Hajime Shibata, Prawal Shrestha, Zhao Li, Trevor C. Caldwell, José B. Silva, Jeffrey C. Gealow
2018	J	`jnl`	A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers. IEEE J. Solid State Circuits QiWei Wang, Hajime Shibata, Antonio Liscidini, Anthony Chan Carusone
2018	—	`conf`	Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS. CICC Yunzhi Dong, José B. Silva, Qingdong Meng, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Donald Paterson, Jeffrey C. Gealow
2018	C	`conf`	Thermal noise limits - ΔΣ vs. pipeline ADCs. ISCAS Hajime Shibata
2017	—	`conf`	16.2 A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving -161dBFS/Hz NSD. ISSCC Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson
2017	J	`jnl`	A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD. IEEE J. Solid State Circuits Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil, Shanthi Pavan
2017	—	`conf`	A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS. CICC QiWei Wang, Hajime Shibata, Anthony Chan Carusone, Antonio Liscidini
2017	—	`conf`	Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS. CICC Yunzhi Dong, José B. Silva, Qingdong Meng, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Donald Paterson, Jeffrey C. Gealow
2017	—	`conf`	High-speed oversampled continuous-time analog-to-digital converters. MWSCAS Trevor C. Caldwell, Hajime Shibata
2016	—	`conf`	15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS. ISSCC Yunzhi Dong, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Richard Schreier, Qingdong Meng, José B. Silva, Donald Paterson, Jeffrey C. Gealow
2016	J	`jnl`	A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS. IEEE J. Solid State Circuits Yunzhi Dong, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Richard Schreier, Qingdong Meng, José B. Silva, Donald Paterson, Jeffrey C. Gealow
2014	—	`conf`	Advances in high-speed continuous-time delta-sigma modulators. CICC Trevor C. Caldwell, David Alldred, Richard Schreier, Hajime Shibata, Yunzhi Dong
2012	J	`jnl`	A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f IEEE J. Solid State Circuits Hajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai
2012	—	`conf`	A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW. ISSCC Hajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai
2010	J	`jnl`	A Frequency Model of a Continuously Driven Clocked CMOS Comparator. IEEE Trans. Circuits Syst. II Express Briefs Shunsuke Okura, Hajime Shibata, Tetsuro Okura, Toru Ido, Kenji Taniguchi
2008	—	`conf`	A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD. ISSCC Wenhua Yang, William Schofield, Hajime Shibata, Sudhir Korrapati, Ali Shaikh, Nazmy Abaskharoun, Dave Ribner
2007	J	`jnl`	Measurement System for Switching Current Distribution in Intrinsic Josephson Junctions. IEICE Trans. Electron. Hiromi Kashiwaya, Tetsuro Matsumoto, Hajime Shibata, Kiyoe Tani, Satoshi Kashiwaya
2006	J	`jnl`	A 375-mW Quadrature Bandpass$\Delta\Sigma$ADC With 8.5-MHz BW and 90-dB DR at 44 MHz. IEEE J. Solid State Circuits Richard Schreier, Nazmy Abaskharoun, Hajime Shibata, Donald Paterson, Steven Rose, Iuri Mehr, Qui Luu
2006	—	`conf`	A 375mW Quadrature Bandpass ΔΣ ADC with 90dB DR and 8.5MHz BW at 44MHz. ISSCC Richard Schreier, Nazmy Abaskharoun, Hajime Shibata, Iuri Mehr, Steve Rose, Donald Paterson
2006	—	`conf`	Frequency Response Analysis of Latch Utilized in High-Speed Comparator. ICECS Shunsuke Okura, Tetsuro Okura, Kenji Taniguchi, Hajime Shibata
2004	J	`jnl`	Controllable decoding for automated analog circuit structure design. Soft Comput. Hajime Shibata, Adrian Stoica, Nobuo Fujii
2003	J	`jnl`	Automated Design of Analog Circuits Using a Cell-Based Structure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hajime Shibata, Soji Mori, Nobuo Fujii
2002	—	`conf`	Automated Design of Analog Circuits Using Cell-Based Structure . Evolvable Hardware Hajime Shibata, Soji Mori, Nobuo Fujii
2001	—	`conf`	Analog circuit synthesis by superimposing of sub-circuits. ISCAS (5) Hajime Shibata, Nobuo Fujii
2000	J	`jnl`	Maintenance of location-dependent views in mobile database environments. Syst. Comput. Jpn. Akira Nakaaki, Hajime Shibata, Toru Murase, Masahiko Tsukamoto, Shojiro Nishio