Hailong Yao - RankMe

86 papers A* 15A 6C 2Journal 31Unranked 32

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Efficient Routing-Based Synthesis for Digital Microfluidic Biochips via Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Biao Liu, Chen Jiang, Qi Xu, Hailong Yao, Tsung-Yi Ho, Bo Yuan
2026	A*	`conf`	Minimum-Cost Network Flow with Dual Predictions. AAAI Zhiyang Chen, Hailong Yao, Xia Yin
2026	J	`jnl`	Minimum-Cost Network Flow with Dual Predictions. CoRR Zhiyang Chen, Hailong Yao, Xia Yin
2025	A*	`conf`	GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs. DAC Mingyang Kou, Weiqing Ji, Shouyi Yin, Hailong Yao
2025	A*	`conf`	Learning Configurations for Data-Driven Multi-Objective Optimization. ICML Zhiyang Chen, Hailong Yao, Xia Yin
2025	A*	`conf`	Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography. DAC Chengkai Wang, Weiqing Ji, Mingyang Kou, Zhiyang Chen, Fei Li, Nengyong Zhu, Hailong Yao
2025	C	`conf`	NaviMap: Partial Order-Guided Neural Architecture via Deep Q-Networks for Efficient CGRA Mapping. ICCD Mingyang Kou, Jun Zeng, Xinyu Peng, Weiqing Ji, Hailong Yao
2025	A*	`conf`	PatLabor: Pareto Optimization of Timing-Driven Routing Trees. DAC Zhiyang Chen, Hailong Yao, Xia Yin
2025	—	`conf`	VAER: Via-Aware Escape Routing for Chiplet Interconnection. ACM Great Lakes Symposium on VLSI Haochang Tian, Weiqing Ji, Mingyang Kou, Chengkai Wang, Fei Li, Hailong Yao
2024	J	`jnl`	GNN-Based Concentration Prediction With Variable Input Flow Rates for Microfluidic Mixers. IEEE Trans. Biomed. Circuits Syst. Weiqing Ji, Xingzhuo Guo, Shouan Pan, Fei Long, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao
2024	J	`jnl`	Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography. CoRR Chengkai Wang, Weiqing Ji, Mingyang Kou, Zhiyang Chen, Fei Li, Hailong Yao
2024	—	`conf`	Supervised Contrastive Learning based Fine-tuning Framework with Small-Scale WSI Dataset on ViT. ICBBT Kenglun Chang, Jintian Ge, Hailong Yao, Yin Xia
2023	—	`conf`	A Compilation Toolchain of Neural Networks for FPGA Backend. ASICON Jun Zeng, Panfeng Wang, Haili Wang, Hailong Yao, Fuchun Sun
2023	J	`jnl`	A Cooperative Multiagent Reinforcement Learning Framework for Droplet Routing in Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen Jiang, Rongquan Yang, Qi Xu, Hailong Yao, Tsung-Yi Ho, Bo Yuan
2023	—	`conf`	GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates. ACM Great Lakes Symposium on VLSI Weiqing Ji, Hailong Yao, Tsung-Yi Ho, Ulf Schlichtmann, Xia Yin
2023	A	`conf`	NeuroEscape: Ordered Escape Routing via Monte-Carlo Tree Search and Neural Network. ICCAD Zhiyang Chen, Tsung-Yi Ho, Ulf Schlichtmann, Datao Chen, Mingyu Liu, Hailong Yao, Xia Yin
2023	—	`conf`	SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips. ACM Great Lakes Symposium on VLSI Weiqing Ji, Xingcheng Yao, Hailong Yao, Tsung-Yi Ho, Ulf Schlichtmann, Xia Yin
2023	J	`jnl`	TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mingyang Kou, Jiangyuan Gu, Hailong Yao, Shaojun Wei, Shouyi Yin
2022	—	`conf`	A Semi-supervised Framework for Automatic Pixel-Wise Breast Cancer Grading of Histological Images. MICAD Kenglun Chang, Yanyuet Man, Hailong Yao
2022	J	`jnl`	Contamination-Aware Synthesis for Programmable Microfluidic Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hui-Chieh Yu, Yu-Huei Lin, Zhiyang Chen, Bing Li, Xing Huang, Ulf Schlichtmann, Tsung-Yi Ho, Hailong Yao
2022	A*	`conf`	GEML: GNN-based efficient mapping method for large loop applications on CGRA. DAC Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao
2022	A*	`conf`	GNN-based concentration prediction for random microfluidic mixers. DAC Weiqing Ji, Xingzhuo Guo, Shouan Pan, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao
2022	—	`conf`	KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference. ACM Great Lakes Symposium on VLSI Jun Zeng, Mingyang Kou, Hailong Yao
2022	A*	`conf`	NeuroSchedule: A Novel Effective GNN-based Scheduling Method for High-level Synthesis. NeurIPS Jun Zeng, Mingyang Kou, Hailong Yao
2021	—	`conf`	Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table. ACM Great Lakes Symposium on VLSI Wei Zhang, Yongxiao Zhou, Tsung-Yi Ho, Hailong Yao
2021	J	`jnl`	DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chunfeng Liu, Xing Huang, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
2021	—	`conf`	Machine Learning Based Acceleration Method for Ordered Escape Routing. ACM Great Lakes Symposium on VLSI Zhiyang Chen, Weiqing Ji, Yihao Peng, Datao Chen, Mingyu Liu, Hailong Yao
2021	J	`jnl`	Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mingyang Kou, Pei-Yi Cheng, Jun Zeng, Tsung-Yi Ho, Kazuyoshi Takagi, Hailong Yao
2020	J	`jnl`	Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qin Wang, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li
2020	J	`jnl`	Lookup Table-Based Fast Reliability-Aware Sample Preparation Using Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lingxuan Shao, Wentai Li, Tsung-Yi Ho, Sudip Roy, Hailong Yao
2020	J	`jnl`	Microfluidic Design for Concentration Gradient Generation Using Artificial Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Weiqing Ji, Tsung-Yi Ho, Junchao Wang, Hailong Yao
2020	J	`jnl`	Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Zhu, Xing Huang, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann
2020	A*	`conf`	TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. DAC Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin
2020	A*	`conf`	Transfer Learning-Based Microfluidic Design System for Concentration Generation∗. DAC Weiqing Ji, Tsung-Yi Ho, Hailong Yao
2020	J	`jnl`	URBER: Ultrafast Rule-Based Escape Routing Method for Large-Scale Sample Delivery Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiayi Weng, Tsung-Yi Ho, Weiqing Ji, Peng Liu, Mengdi Bao, Hailong Yao
2019	—	`conf`	Automatic Breast Cancer Grading of Histological Images using Dilated Residual Network. ICBBT Yanyuet Man, Hailong Yao
2019	J	`jnl`	Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qinghang Zhao, Wenyu Sun, Jiaqing Zhao, Jian Zhao, Hailong Yao, Tsung-Yi Ho, Xiaojun Guo, Huazhong Yang, Yongpan Liu
2018	—	`conf`	A Comprehensive Security System for Digital Microfluidic Biochips. ITC-Asia Chun-Yu Lin, Juinn-Dar Huang, Hailong Yao, Tsung-Yi Ho
2018	J	`jnl`	AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kailin Yang, Hailong Yao, Tsung-Yi Ho, Kunze Xin, Yici Cai
2018	—	`conf`	More Effective Randomly-Designed Microfluidics. ISVLSI Weiqing Ji, Tsung-Yi Ho, Hailong Yao
2018	A	`conf`	Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips. ICCAD Ying Zhu, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann
2018	J	`jnl`	Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qin Wang, Hao Zou, Hailong Yao, Tsung-Yi Ho, Robert Wille, Yici Cai
2018	J	`jnl`	Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits. ACM Trans. Design Autom. Electr. Syst. Hongxia Zhou, Chiu-Wing Sham, Hailong Yao
2017	—	`conf`	Close-to-optimal placement and routing for continuous-flow microfluidic biochips. ASP-DAC Andreas Grimmer, Qin Wang, Hailong Yao, Tsung-Yi Ho, Robert Wille
2017	A*	`conf`	Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture. DAC Qinghang Zhao, Yongpan Liu, Wenyu Sun, Jiaqing Zhao, Hailong Yao, Xiaojun Guo, Huazhong Yang
2017	—	`conf`	Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. ASP-DAC Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
2017	—	`conf`	LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips. ACM Great Lakes Symposium on VLSI Lingxuan Shao, Yibin Yang, Hailong Yao, Tsung-Yi Ho, Yici Cai
2017	J	`jnl`	Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. Qin Wang, Yue Xu, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
2017	J	`jnl`	Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. CoRR Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
2017	A*	`conf`	Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. DAC Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
2016	A	`conf`	Control-fluidic CoDesign for paper-based digital microfluidic biochips. ICCAD Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai
2016	J	`jnl`	Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hailong Yao, Qin Wang, Yiren Shen, Tsung-Yi Ho, Yici Cai
2016	—	`conf`	Sequence-pair-based placement and routing for flow-based microfluidic biochips. ASP-DAC Qin Wang, Yizhong Ru, Hailong Yao, Tsung-Yi Ho, Yici Cai
2015	J	`jnl`	Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic Biochips. IEEE Des. Test Hailong Yao, Qin Wang, Yizhong Ru, Yici Cai, Tsung-Yi Ho
2015	J	`jnl`	Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. IEEE Trans. Very Large Scale Integr. Syst. Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze
2015	A*	`conf`	PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips. DAC Hailong Yao, Tsung-Yi Ho, Yici Cai
2015	J	`jnl`	SIAR: Customized real-time interactive router for analog circuits. Integr. Hailong Yao, Fan Yang, Yici Cai, Qiang Zhou, Chiu-Wing Sham
2015	—	`conf`	SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips. ISPD Qin Wang, Weiran He, Hailong Yao, Tsung-Yi Ho, Yici Cai
2014	J	`jnl`	Fast and scalable parallel layout decomposition in double patterning lithography. Integr. Wei Zhao, Hailong Yao, Yici Cai, Subarna Sinha, Charles C. Chiang
2014	J	`jnl`	Length matching in detailed routing for analog and mixed signal circuits. Microelectron. J. Hailong Yao, Qiang Gao, Yici Cai, Qiang Zhou, Chiu-Wing Sham
2014	A*	`conf`	Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips. DAC Qin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai
2014	—	`conf`	Slicing Floorplans with Handling Symmetry and General Placement Constraints. ISVLSI Hongxia Zhou, Chiu-Wing Sham, Hailong Yao
2013	—	`conf`	A new splitting graph construction algorithm for SIAR router. ASICON Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou
2013	—	`conf`	Analog routing considering min-area constraint. ASICON Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou
2013	—	`conf`	SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography. ISQED Zihao Chen, Hailong Yao, Yici Cai
2012	—	`conf`	LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits. ASP-DAC Hailong Yao, Yici Cai, Qiang Gao
2011	—	`conf`	A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits. ISQED Qiang Gao, Hailong Yao, Qiang Zhou, Yici Cai
2011	—	`conf`	A novel fine-grain track routing approach for routability and crosstalk optimization. ISQED Zhongdong Qi, Qiang Zhou, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao
2011	—	`conf`	Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. ISVLSI Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai
2011	—	`conf`	Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze
2011	—	`conf`	SIAR: splitting-graph-based interactive analog router. ACM Great Lakes Symposium on VLSI Fan Yang, Hailong Yao, Qiang Zhou, Yici Cai
2010	A	`conf`	Analog circuit shielding routing algorithm based on net classification. ISLPED Qiang Gao, Yin Shen, Yici Cai, Hailong Yao
2010	J	`jnl`	Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao
2010	J	`jnl`	Layout Decomposition Approaches for Double Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao
2009	—	`conf`	Revisiting the linear programming framework for leakage power vs. performance optimization. ISQED Kwangok Jeong, Andrew B. Kahng, Hailong Yao
2008	A*	`conf`	Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. DAC Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao
2008	J	`jnl`	Efficient range pattern matching algorithm for process-hotspot detection. IET Circuits Devices Syst. Hailong Yao, Subarna Sinha, Jingyu Xu, Charles C. Chiang, Yici Cai, Xianlong Hong
2008	A	`conf`	Layout decomposition for double patterning lithography. ICCAD Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao
2007	—	`conf`	CMP-aware Maze Routing Algorithm for Yield Enhancement. ISVLSI Hailong Yao, Yici Cai, Xianlong Hong
2006	C	`conf`	Congestion-driven W-shape multilevel full-chip routing framework. ISCAS Hailong Yao, Yici Cai, Xianlong Hong
2006	—	`conf`	DFM-aware Routing for Yield Enhancement. APCCAS Xianlong Hong, Yici Cai, Hailong Yao, Duo Li
2006	A	`conf`	Efficient process-hotspot detection using range pattern matching. ICCAD Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai
2006	J	`jnl`	Multilevel Routing With Redundant Via Insertion. IEEE Trans. Circuits Syst. II Express Briefs Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
2005	J	`jnl`	Crosstalk-Aware Routing Resource Assignment. J. Comput. Sci. Technol. Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
2005	—	`conf`	Improved multilevel routing with redundant via placement for yield and reliability. ACM Great Lakes Symposium on VLSI Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou
2004	—	`conf`	Crosstalk driven routing resource assignment. ISCAS (5) Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai