Haile Yu

12 papers A 2B 4Journal 1Unranked 5
YearRankTypeTitle / Venue / Authors
2012 J jnl
An FPGA Chip Identification Generator Using Configurable Ring Oscillators.
IEEE Trans. Very Large Scale Integr. Syst.
Haile Yu, Philip Heng Wai Leong, Qiang Xu
2012 — conf
CODA: A concurrent online delay measurement architecture for critical paths.
ASP-DAC
Yubin Zhang, Haile Yu, Qiang Xu
2012 — conf
HTOutlier: Hardware Trojan detection with side-channel signature outlier identification.
HOST
Jie Zhang, Haile Yu, Qiang Xu
2011 B conf
On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry.
FPL
Haile Yu, Qiang Xu, Philip Heng Wai Leong
2011 A conf
On timing yield improvement for FPGA designs using architectural symmetry (abstract only).
FPGA
Haile Yu, Qiang Xu, Philip Heng Wai Leong
2010 — conf
An FPGA chip identification generator using configurable ring oscillator.
FPT
Haile Yu, Philip Heng Wai Leong, Qiang Xu
2010 — conf
Fine-grained characterization of process variation in FPGAs.
FPT
Haile Yu, Qiang Xu, Philip Heng Wai Leong
2009 — conf
A detailed delay path model for FPGAs.
FPT
Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong
2009 B conf
Towards a unique FPGA-based identification circuit using process variations.
FPL
Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf
2008 A conf
FPGA interconnect design using logical effort.
FPGA
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
2008 B conf
FPGA interconnect design using logical effort.
FPL
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
2008 B conf
FPGA interconnect sizing using extended logical effort model.
FPL
Haile Yu