Hai Zhou - RankMe

218 papers A* 22A 50B 1C 7Misc 2Journal 77Unranked 53

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	LLA: Enhancing Security and Privacy for Generative Models with Logic-Locked Accelerators. AAAI You Li, Guannan Zhao, Yuhao Ju, Yunqi He, Jie Gu, Hai Zhou
2025	J	`jnl`	An Efficient Placement Speedup Technique Based on Graph Signal Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2025	A	`conf`	DE2: SAT-Based Sequential Logic Decryption with a Functional Description. DATE You Li, Guannan Zhao, Yunqi He, Hai Zhou
2025	J	`jnl`	LLA: Enhancing Security and Privacy for Generative Models with Logic-Locked Accelerators. CoRR You Li, Guannan Zhao, Yuhao Ju, Yunqi He, Jie Gu, Hai Zhou
2025	A*	`conf`	RE3: Finding Refinement Relations with Relational Mapping Abstraction. DAC You Li, Guannan Zhao, Yunqi He, Hai Zhou
2025	J	`jnl`	The Power of Graph Signal Processing for Chip Placement Acceleration. CoRR Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2024	J	`jnl`	Certifying Global Robustness for Deep Neural Networks. CoRR You Li, Guannan Zhao, Shuyu Kong, Yunqi He, Hai Zhou
2024	A*	`conf`	Evaluating the Security of Logic Locking on Deep Neural Networks. DAC You Li, Guannan Zhao, Yunqi He, Hai Zhou
2024	J	`jnl`	Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. IEEE Trans. Very Large Scale Integr. Syst. Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2024	—	`conf`	Multimodal Bayesian Networks for Automatic Skin Disease Diagnosis. BIBM Yunqi He, Jiahe Liu, You Li, Hai Zhou, Linglong Cai, Taimei Cui
2024	—	`conf`	Property Guided Secure Configuration Space Search. ISC (2) You Li, Kaiyu Hou, Yunqi He, Yan Chen, Hai Zhou
2024	A	`conf`	The Power of Graph Signal Processing for Chip Placement Acceleration. ICCAD Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2023	—	`conf`	A Combination of DNN and BN for Automatic Skin Disease Diagnosis. ISBI Yunqi He, Linglong Cai, Taimei Cui, You Li, Hai Zhou
2023	J	`jnl`	GraphPlanner: Floorplanning with Graph Neural Network. ACM Trans. Design Autom. Electr. Syst. Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2023	J	`jnl`	Guest Editor's Introduction: Machine Learning for VLSI Physical Design. ACM Trans. Design Autom. Electr. Syst. Igor L. Markov, Fan Yang, Li Shang, Hai Zhou
2023	A	`conf`	ObfusLock: An Efficient Obfuscated Locking Framework for Circuit IP Protection DATE You Li, Guannan Zhao, Yunqi He, Hai Zhou
2023	A*	`conf`	SE3: Sequential Equivalence Checking for Non-Cycle-Accurate Design Transformations DAC You Li, Guannan Zhao, Yunqi He, Hai Zhou
2022	A*	`conf`	Floorplanning with graph attention. DAC Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2022	—	`conf`	Global Attack and Remedy on IC-Specific Logic Encryption. HOST Amin Rezaei, Ava Hedayatipour, Hossein Sayadi, Mehrdad Aliasgari, Hai Zhou
2022	J	`jnl`	Incentivizing Federated Learning. CoRR Shuyu Kong, You Li, Hai Zhou
2021	A	`conf`	Discovering emergency call pitfalls for cellular networks with formal methods. MobiSys Kaiyu Hou, You Li, Yinbo Yu, Yan Chen, Hai Zhou
2021	J	`jnl`	Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries. IACR Cryptol. ePrint Arch. Amin Rezaei, Jie Gu, Hai Zhou
2021	A	`conf`	Sequential Logic Encryption Against Model Checking Attack. DATE Amin Rezaei, Hai Zhou
2021	J	`jnl`	Sequential Logic Encryption Against Model Checking Attack. IACR Cryptol. ePrint Arch. Amin Rezaei, Hai Zhou
2020	J	`jnl`	Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks
2020	J	`jnl`	KNN-enhanced Deep Learning Against Noisy Labels. CoRR Shuyu Kong, You Li, Jia Wang, Amin Rezaei, Hai Zhou
2020	—	`conf`	Network protocol safe configuration search in one shot. SIGCOMM Posters and Demos You Li, Kaiyu Hou, Hai Zhou, Yan Chen
2020	A	`conf`	Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation. DATE Amin Rezaei, Yuanqi Shen, Hai Zhou
2019	A	`conf`	An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel. DATE Xin Wei, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2019	J	`jnl`	BeSAT: Behavioral SAT-based Attack on Cyclic Logic Encryption. IACR Cryptol. ePrint Arch. Yuanqi Shen, You Li, Amin Rezaei, Shuyu Kong, David Dlott, Hai Zhou
2019	—	`conf`	BeSAT: behavioral SAT-based attack on cyclic logic encryption. ASP-DAC Yuanqi Shen, You Li, Amin Rezaei, Shuyu Kong, David Dlott, Hai Zhou
2019	—	`conf`	CellScope: Automatically Specifying and Verifying Cellular Network Protocols. SIGCOMM Posters and Demos Yinbo Yu, You Li, Kaiyu Hou, Yan Chen, Hai Zhou, Jianfeng Yang
2019	J	`jnl`	CycSAT-Unresolvable Cyclic Logic Encryption Using Unreachable States. IACR Cryptol. ePrint Arch. Amin Rezaei, You Li, Yuanqi Shen, Shuyu Kong, Hai Zhou
2019	—	`conf`	CycSAT-unresolvable cyclic logic encryption using unreachable states. ASP-DAC Amin Rezaei, You Li, Yuanqi Shen, Shuyu Kong, Hai Zhou
2019	A*	`conf`	Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing. DAC Zhengyu Chen, Hai Zhou, Jie Gu
2019	J	`jnl`	R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. IEEE Trans. Very Large Scale Integr. Syst. Zhengyu Chen, Hai Zhou, Jie Gu
2019	J	`jnl`	Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation. IACR Cryptol. ePrint Arch. Amin Rezaei, Yuanqi Shen, Hai Zhou
2019	A	`conf`	Resolving the Trilemma in Logic Encryption. ICCAD Hai Zhou, Amin Rezaei, Yuanqi Shen
2019	J	`jnl`	Resolving the Trilemma in Logic Encryption. IACR Cryptol. ePrint Arch. Hai Zhou, Amin Rezaei, Yuanqi Shen
2019	A	`conf`	SigAttack: New High-level SAT-based Attack on Logic Encryptions. DATE Yuanqi Shen, You Li, Shuyu Kong, Amin Rezaei, Hai Zhou
2019	J	`jnl`	SigAttack: New High-level SAT-based Attack on Logic Encryptions. IACR Cryptol. ePrint Arch. Yuanqi Shen, You Li, Shuyu Kong, Amin Rezaei, Hai Zhou
2019	J	`jnl`	Vulnerability and Remedy of Stripped Function Logic Locking. IACR Cryptol. ePrint Arch. Hai Zhou, Yuanqi Shen, Amin Rezaei
2018	—	`conf`	A comparative investigation of approximate attacks on logic encryptions. ASP-DAC Yuanqi Shen, Amin Rezaei, Hai Zhou
2018	J	`jnl`	An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis. ACM Trans. Design Autom. Electr. Syst. Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Hai Zhou, Xuan Zeng
2018	J	`jnl`	Chapter Three - Multiobjectivism in Dark Silicon Age. Adv. Comput. Amin Rezaei, Masoud Daneshtalab, Hai Zhou
2018	J	`jnl`	Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. IEEE Trans. Very Large Scale Integr. Syst. Ye Zhang, Wenlong Lyu, Wai-Shing Luk, Fan Yang, Hai Zhou, Dian Zhou, David Z. Pan, Xuan Zeng
2018	A	`conf`	Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks. DATE Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou
2018	J	`jnl`	Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design. IEEE Trans. Very Large Scale Integr. Syst. Shuyu Kong, Hai Zhou, Jie Gu
2018	C	`conf`	R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. ICCD Zhengyu Chen, Hai Zhou, Jie Gu
2018	A	`conf`	SAT-based bit-flipping attack on logic encryptions. DATE Yuanqi Shen, Amin Rezaei, Hai Zhou
2017	J	`jnl`	A Comparative Investigation of Approximate Attacks on Logic Encryptions. IACR Cryptol. ePrint Arch. Yuanqi Shen, Amin Rezaei, Hai Zhou
2017	J	`jnl`	A Humble Theory and Application for Logic Encryption. IACR Cryptol. ePrint Arch. Hai Zhou
2017	—	`conf`	A Novel N-Retry Transactional Memory Model for Multi-Thread Programming. ISPA/IUCC Kun Lu, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2017	J	`jnl`	An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. ACM Trans. Design Autom. Electr. Syst. Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng
2017	—	`conf`	An efficient algorithm for stencil planning and optimization in E-beam lithography. ASP-DAC Jiabei Ge, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2017	J	`jnl`	CycSAT: SAT-Based Attack on Cyclic Logic Encryptions. IACR Cryptol. ePrint Arch. Hai Zhou, Ruifeng Jiang, Shuyu Kong
2017	A	`conf`	CycSAT: SAT-based attack on cyclic logic encryptions. ICCAD Hai Zhou, Ruifeng Jiang, Shuyu Kong
2017	J	`jnl`	Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks. IACR Cryptol. ePrint Arch. Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou
2017	—	`conf`	Double DIP: Re-Evaluating Security of Logic Encryption Algorithms. ACM Great Lakes Symposium on VLSI Yuanqi Shen, Hai Zhou
2017	J	`jnl`	Double DIP: Re-Evaluating Security of Logic Encryption Algorithms. IACR Cryptol. ePrint Arch. Yuanqi Shen, Hai Zhou
2017	—	`conf`	Memristor-Based Clock Design and Optimization with In-Situ Tunability. ISVLSI Shuyu Kong, Jie Gu, Hai Zhou
2017	C	`conf`	Multi-objective Task Mapping Approach for Wireless NoC in Dark Silicon Age. PDP Amin Rezaei, Dan Zhao, Masoud Daneshtalab, Hai Zhou
2017	—	`conf`	Network flow based cut redistribution and insertion for advanced 1D layout design. ASP-DAC Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2017	J	`jnl`	SAT-based Bit-flipping Attack on Logic Encryptions. IACR Cryptol. ePrint Arch. Yuanqi Shen, Amin Rezaei, Hai Zhou
2017	—	`conf`	Using Security Invariant To Verify Confidentiality in Hardware Design. ACM Great Lakes Symposium on VLSI Shuyu Kong, Yuanqi Shen, Hai Zhou
2016	J	`jnl`	Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng
2015	J	`jnl`	Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. ACM Trans. Design Autom. Electr. Syst. Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng
2015	—	`conf`	Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography. ASP-DAC Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou
2015	J	`jnl`	Multi-parameter clock skew scheduling. Integr. Xingbao Zhou, Wai-Shing Luk, Hai Zhou, Fan Yang, Changhao Yan, Xuan Zeng
2015	—	`conf`	Synthesis of resilient circuits from guarded atomic actions. ASP-DAC Yuankai Chen, Hai Zhou
2014	J	`jnl`	Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xingbao Zhou, Fan Yang, Hai Zhou, Min Gong, Hengliang Zhu, Ye Zhang, Xuan Zeng
2014	A	`conf`	On error modeling and analysis of approximate adders. ICCAD Li Li, Hai Zhou
2014	J	`jnl`	Optimal and Efficient Algorithms for Multidomain Clock Skew Scheduling. IEEE Trans. Very Large Scale Integr. Syst. Li Li, Yinghai Lu, Hai Zhou
2014	A	`conf`	Recovery-based resilient latency-insensitive systems. DATE Yuankai Chen, Xuan Zeng, Hai Zhou
2013	J	`jnl`	An efficient method for gradient-aware dummy fill synthesis. Integr. Peng Wu, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng
2013	J	`jnl`	Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jie Wu, Jia Wang, Kun Li, Hai Zhou, Qin Lv, Li Shang, Yihe Sun
2013	A	`conf`	Layout decomposition with pairwise coloring for multiple patterning lithography. ICCAD Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng
2013	J	`jnl`	Post-routing layer assignment for double patterning with timing critical paths consideration. Integr. Jian Sun, Yinghai Lu, Hai Zhou, Changhao Yan, Xuan Zeng
2013	A	`conf`	Resource-constrained high-level datapath optimization in ASIP design. DATE Yuankai Chen, Hai Zhou
2013	A	`conf`	Retiming for Soft Error Minimization Under Error-Latching Window Constraints. DATE Yinghai Lu, Hai Zhou
2013	J	`jnl`	SmipRef: An efficient method for multi-domain clock skew scheduling. Integr. Yanling Zhi, Wai-Shing Luk, Hai Zhou, Xuan Zeng
2013	—	`conf`	Structural transformation for best-possible obfuscation of sequential circuits. HOST Li Li, Hai Zhou
2012	A	`conf`	An efficient algorithm for library-based cell-type selection in high-performance low-power designs. ICCAD Li Li, Peng Kang, Yinghai Lu, Hai Zhou
2012	—	`conf`	Buffer minimization in pipelined SDF scheduling on multi-core platforms. ASP-DAC Yuankai Chen, Hai Zhou
2012	A	`conf`	Clock skew scheduling for timing speculation. DATE Rong Ye, Feng Yuan, Hai Zhou, Qiang Xu
2012	A	`conf`	Efficient design space exploration for component-based system design. ICCAD Yinghai Lu, Hai Zhou
2012	—	`conf`	Optimal prescribed-domain clock skew scheduling. ASP-DAC Li Li, Yinghai Lu, Hai Zhou
2011	J	`jnl`	A Special Section on Multicore Parallel CAD: Algorithm Design and Programming. ACM Trans. Design Autom. Electr. Syst. Kurt Keutzer, Peng Li, Li Shang, Hai Zhou
2011	—	`conf`	A practical method for multi-domain clock skew optimization. ASP-DAC Yanling Zhi, Hai Zhou, Xuan Zeng
2011	A	`conf`	An efficient algorithm for multi-domain clock skew scheduling. DATE Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng
2011	J	`jnl`	Binning Optimization for Transparently-Latched Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Min Gong, Hai Zhou, Li Li, Jun Tao, Xuan Zeng
2011	J	`jnl`	Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng
2011	J	`jnl`	FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack
2011	A	`conf`	Integrated circuit white space redistribution for temperature optimization. DATE Yuankai Chen, Hai Zhou, Robert P. Dick
2011	—	`conf`	Low power discrete voltage assignment under clock skew scheduling. ASP-DAC Li Li, Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng
2011	J	`jnl`	MSV-Driven Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qiang Ma, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou
2011	A*	`conf`	Optimal multi-domain clock skew scheduling. DAC Li Li, Yinghai Lu, Hai Zhou
2011	—	`conf`	Parallel cross-layer optimization of high-level synthesis and physical design. ASP-DAC James Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng
2011	—	`conf`	Post-routing layer assignment for double patterning. ASP-DAC Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng
2010	A	`conf`	Hybrid energy storage system integration for vehicles. ISLPED Jia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang
2010	J	`jnl`	Multicore Parallelization of Min-Cost Flow for CAD Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng
2010	J	`jnl`	Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou
2010	—	`conf`	iRetILP: an efficient incremental algorithm for min-period retiming under general delay model. ASP-DAC Debasish Das, Jia Wang, Hai Zhou
2009	J	`jnl`	A Timing-Dependent Power Estimation Framework Considering Coupling. IEEE Trans. Very Large Scale Integr. Syst. DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail
2009	J	`jnl`	ACM Transactions on Design Automation of Electronic Systems (TODAES) special section call for papers: Parallel CAD: Algorithm design and programming. ACM Trans. Design Autom. Electr. Syst. Kurt Keutzer, Peng Li, Li Shang, Hai Zhou
2009	—	`conf`	An efficient current-based logic cell model for crosstalk delay analysis. ISQED Debasish Das, William Scott, Shahin Nazarian, Hai Zhou
2009	A	`conf`	Binning optimization based on SSTA for transparently-latched circuits. ICCAD Min Gong, Hai Zhou, Jun Tao, Xuan Zeng
2009	—	`conf`	Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. ASP-DAC Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee
2009	A	`conf`	Exception triggered DoS attacks on wireless networks. DSN Yao Zhao, Sagar Vemuri, Jiazhen Chen, Yan Chen, Hai Zhou, Zhi Fu
2009	—	`conf`	Exploring adjacency in floorplanning. ASP-DAC Jia Wang, Hai Zhou
2009	J	`jnl`	Gate Sizing by Lagrangian Relaxation Revisited. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jia Wang, Debasish Das, Hai Zhou
2009	A*	`conf`	Multicore parallel min-cost flow algorithm for CAD applications. DAC Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng
2009	A*	`conf`	Provably good and practically efficient algorithms for CMP dummy fill. DAC Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng
2009	B	`conf`	Retiming and resynthesis with sweep are complete for sequential transformation. FMCAD Hai Zhou
2009	—	`conf`	Risk aversion min-period retiming under process variations. ASP-DAC Jia Wang, Hai Zhou
2009	A*	`conf`	Statistical reliability analysis under process variation and aging effects. DAC Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng
2008	—	`conf`	A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications. ASP-DAC Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee
2008	J	`jnl`	A new efficient retiming algorithm derived by formal manipulation. ACM Trans. Design Autom. Electr. Syst. Hai Zhou
2008	—	`conf`	An ISPD Jieyi Long, Hai Zhou, Seda Ogrenci Memik
2008	A*	`conf`	An efficient incremental algorithm for min-area retiming. DAC Jia Wang, Hai Zhou
2008	—	`ch.`	Circuit Retiming. Encyclopedia of Algorithms Hai Zhou
2008	—	`ch.`	Circuit Retiming: An Incremental Approach. Encyclopedia of Algorithms Hai Zhou
2008	J	`jnl`	EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jieyi Long, Hai Zhou, Seda Ogrenci Memik
2008	J	`jnl`	Fast Estimation of Timing Yield Bounds for Process Variations. IEEE Trans. Very Large Scale Integr. Syst. Ruiming Chen, Hai Zhou
2008	A	`conf`	Linear constraint graph for floorplan optimization with soft blocks. ICCAD Jia Wang, Hai Zhou
2008	J	`jnl`	Optimizing wirelength and routability by searching alternative packings in floorplanning. ACM Trans. Design Autom. Electr. Syst. Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou
2008	—	`conf`	Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ASP-DAC Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou
2008	—	`ch.`	Rectilinear Spanning Tree. Encyclopedia of Algorithms Hai Zhou
2008	—	`ch.`	Rectilinear Steiner Tree. Encyclopedia of Algorithms Hai Zhou
2008	Misc	`conf`	State space abstraction for parameterized self-stabilizing embedded systems. EMSOFT Nikolaos D. Liveris, Hai Zhou, Robert P. Dick, Prithviraj Banerjee
2007	A	`conf`	3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou
2007	—	`conf`	Address generation for nanowire decoders. ACM Great Lakes Symposium on VLSI Jia Wang, Ming-Yang Kao, Hai Zhou
2007	J	`jnl`	Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debjit Sinha, Hai Zhou, Narendra V. Shenoy
2007	J	`jnl`	An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ruiming Chen, Hai Zhou
2007	—	`conf`	Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains. ASP-DAC Chuan Lin, Hai Zhou
2007	A	`conf`	Design closure driven delay relaxation based on convex cost network flow. DATE Chuan Lin, Aiguo Xie, Hai Zhou
2007	—	`conf`	Fast Buffer Insertion for Yield Optimization Under Process Variations. ASP-DAC Ruiming Chen, Hai Zhou
2007	A*	`conf`	Fast Min-Cost Buffer Insertion under Process Variations. DAC Ruiming Chen, Hai Zhou
2007	A	`conf`	Gate sizing by Lagrangian relaxation revisited. ICCAD Jia Wang, Debasish Das, Hai Zhou
2007	Misc	`conf`	Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
2007	J	`jnl`	Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou
2007	—	`conf`	New Block-Based Statistical Timing Analysis Approaches Without Moment Matching. ASP-DAC Ruiming Chen, Hai Zhou
2007	—	`conf`	NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. ACM Great Lakes Symposium on VLSI Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack
2007	J	`jnl`	Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jia Wang, Hai Zhou
2007	—	`ed.`	Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007 ACM Great Lakes Symposium on VLSI Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud
2007	—	`conf`	Retiming for Synchronous Data Flow Graphs. ASP-DAC Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee
2007	A	`conf`	Timing budgeting under arbitrary process variations. ICCAD Ruiming Chen, Hai Zhou
2007	J	`jnl`	Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuan Lin, Hai Zhou
2007	J	`jnl`	Unified Incremental Physical-Level and High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou
2006	A	`conf`	A revisit to floorplan optimization by Lagrangian relaxation. ICCAD Chuan Lin, Hai Zhou, Chris C. N. Chu
2006	A	`conf`	A timing dependent power estimation framework considering coupling. ICCAD Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou
2006	—	`conf`	Advances in Computation of the Maximum of a Set of Random Variables. ISQED Debjit Sinha, Hai Zhou, Narendra V. Shenoy
2006	J	`jnl`	An Efficient Data Structure for Maxplus Merge in Dynamic Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ruiming Chen, Hai Zhou
2006	A*	`conf`	An efficient retiming algorithm under setup and hold constraints. DAC Chuan Lin, Hai Zhou
2006	J	`jnl`	Clustering for Processing Rate Optimization. IEEE Trans. Very Large Scale Integr. Syst. Chuan Lin, Jia Wang, Hai Zhou
2006	C	`conf`	FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. ICCD Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack
2006	J	`jnl`	Gate-size optimization under timing constraints for coupling-noise reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debjit Sinha, Hai Zhou
2006	A*	`conf`	Optimal jumper insertion for antenna avoidance under ratio upper-bound. DAC Jia Wang, Hai Zhou
2006	J	`jnl`	Optimal wire retiming without binary search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuan Lin, Hai Zhou
2006	—	`ed.`	Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006 ACM Great Lakes Symposium on VLSI Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou
2006	—	`conf`	Processing Rate Optimization by Sequential System Floorplanning. ISQED Jia Wang, Hai Zhou, Ping-Chih Wu
2006	A	`conf`	Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. DATE Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou
2006	J	`jnl`	Statistical Timing Analysis With Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debjit Sinha, Hai Zhou
2006	J	`jnl`	Statistical Timing Yield Optimization by Gate Sizing. IEEE Trans. Very Large Scale Integr. Syst. Debjit Sinha, Narendra V. Shenoy, Hai Zhou
2006	J	`jnl`	Statistical timing verification for transparently latched circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ruiming Chen, Hai Zhou
2006	A*	`conf`	Yield-Aware Cache Architectures. MICRO Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou
2005	A	`conf`	A unified framework for statistical timing analysis with coupling and multiple input switching. ICCAD Debjit Sinha, Hai Zhou
2005	—	`conf`	An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. Asian Test Symposium Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee
2005	A	`conf`	Clustering for processing rate optimization. ICCAD Chuan Lin, Jia Wang, Hai Zhou
2005	—	`conf`	Deriving a new efficient algorithm for min-period retiming. ASP-DAC Hai Zhou
2005	A	`conf`	Efficient algorithms for buffer insertion in general circuits based on network flow. ICCAD Ruiming Chen, Hai Zhou
2005	A*	`conf`	Incremental exploration of the combined physical and behavioral design space. DAC Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou
2005	—	`conf`	Interconnect estimation without packing via ACG floorplans. ASP-DAC Jia Wang, Hai Zhou
2005	A*	`conf`	Leakage power optimization with dual-V DAC Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee
2005	J	`jnl`	Spanning graph-based nonrectilinear steiner tree algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
2005	A	`conf`	Statistical gate sizing for timing yield optimization. ICCAD Debjit Sinha, Narendra V. Shenoy, Hai Zhou
2005	—	`conf`	Timing yield estimation using statistical static timing analysis. ISCAS (3) Min Pan, Chris C. N. Chu, Hai Zhou
2005	A	`conf`	Trade-off between latch and flop for min-period sequential circuit designs with crosstalk. ICCAD Chuan Lin, Hai Zhou
2005	J	`jnl`	Wire retiming as fixpoint computation. IEEE Trans. Very Large Scale Integr. Syst. Chuan Lin, Hai Zhou
2005	—	`conf`	Yield driven gate sizing for coupling-noise reduction under uncertainty. ASP-DAC Debjit Sinha, Hai Zhou
2004	C	`conf`	A Flexible Data Structure for Efficient Buffer Insertion. ICCD Ruiming Chen, Hai Zhou
2004	C	`conf`	ACG-Adjacent Constraint Graph for General Floorplans. ICCD Hai Zhou, Jia Wang
2004	A	`conf`	Clock schedule verification under process variations. ICCAD Ruiming Chen, Hai Zhou
2004	J	`jnl`	Efficient Steiner tree construction based on spanning graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hai Zhou
2004	—	`conf`	Efficient octilinear Steiner tree construction based on spanning graphs. ASP-DAC Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
2004	A	`conf`	Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. ICCAD Debjit Sinha, Hai Zhou
2004	—	`conf`	Minimal period retiming under process variations. ACM Great Lakes Symposium on VLSI Jia Wang, Hai Zhou
2004	—	`conf`	Optimal gate sizing for coupling-noise reduction. ISPD Debjit Sinha, Hai Zhou, Chris C. N. Chu
2004	A	`conf`	Optimal wire retiming without binary search. ICCAD Chuan Lin, Hai Zhou
2004	J	`jnl`	Retiming for wire pipelining in system-on-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hai Zhou, Chuan Lin
2004	A	`conf`	Timing macro-modeling of IP blocks with crosstalk. ICCAD Ruiming Chen, Hai Zhou
2004	A	`conf`	Wire Retiming for System-on-Chip by Fixpoint Computation. DATE Chuan Lin, Hai Zhou
2003	J	`jnl`	BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. Formal Methods Syst. Des. Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal
2003	—	`conf`	Efficient Steiner tree construction based on spanning graphs. ISPD Hai Zhou
2003	—	`conf`	Interconnect-driven floorplanning by searching alternative packings. ASP-DAC Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou
2003	A	`conf`	Retiming for Wire Pipelining in System-On-Chip. ICCAD Chuan Lin, Hai Zhou
2003	A	`conf`	Timing Verification with Crosstalk for Transparently Latched Circuits. DATE Hai Zhou
2003	J	`jnl`	Timing analysis with crosstalk is a fixpoint on a complete lattice. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hai Zhou
2002	—	`conf`	Clock schedule verification with crosstalk. Timing Issues in the Specification and Synthesis of Digital Systems Hai Zhou
2002	J	`jnl`	Efficient minimum spanning tree construction without Delaunay triangulation. Inf. Process. Lett. Hai Zhou, Narendra V. Shenoy, William Nicholls
2002	A	`conf`	Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou
2001	J	`jnl`	Buffer minimization in pass transistor logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hai Zhou, Adnan Aziz
2001	—	`conf`	Efficient minimum spanning tree construction without Delaunay triangulation. ASP-DAC Hai Zhou, Narendra V. Shenoy, William Nicholls
2001	A*	`conf`	Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. DAC Hai Zhou, Narendra V. Shenoy, William Nicholls
2000	—	`conf`	Buffer minimization in pass transistor logic. ISPD Hai Zhou, Adnan Aziz
2000	A*	`conf`	Optimal low power X OR gate decomposition. DAC Hai Zhou, D. F. Wong
2000	J	`jnl`	Simultaneous routing and buffer insertion with restrictions onbuffer locations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz
1999	C	`conf`	An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou
1999	J	`jnl`	Global routing with crosstalk constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hai Zhou, Martin D. F. Wong
1999	A	`conf`	Integrated floorplanning and interconnect planning. ICCAD Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
1999	A*	`conf`	Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz
1998	A*	`conf`	BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. CAV Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal
1998	A*	`conf`	Global Routing with Crosstalk Constraints. DAC Hai Zhou, D. F. Wong
1998	J	`jnl`	Optimal river routing with crosstalk constraints. ACM Trans. Design Autom. Electr. Syst. Hai Zhou, D. F. Wong
1997	A	`conf`	An exact gate decomposition algorithm for low-power technology mapping. ICCAD Hai Zhou, D. F. Wong
1997	C	`conf`	Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. ICCD Hai Zhou, D. F. Wong
1996	A	`conf`	An optimal algorithm for river routing with crosstalk constraints. ICCAD Hai Zhou, D. F. Wong
1996	A	`conf`	Optimal non-uniform wire-sizing under the Elmore delay model. ICCAD Chung-Ping Chen, Hai Zhou, D. F. Wong