Hafiz Md. Hasan Babu

68 papers C 11Misc 10Journal 23Unranked 23

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Quantum Meets AI: Pioneering the Future of Intelligent Technology of Multiple-Valued Logic. IEEE Access Hafiz Md. Hasan Babu
2024	J	`jnl`	A comprehensive approach to detecting chemical adulteration in fruits using computer vision, deep learning, and chemical sensors. Intell. Syst. Appl. Abdus Sattar, Md. Asif Mahmud Ridoy, Aloke Kumar Saha, Hafiz Md. Hasan Babu, Mohammad Nurul Huda
2024	—	`book`	DNA Logic Design - Computing with DNA DNA Logic Design Hafiz Md. Hasan Babu
2023	J	`jnl`	Prevention of shoulder-surfing attacks using shifting condition using digraph substitution rules. CoRR Amanul Islam, Fazidah Othman, Nazmus Sakib, Hafiz Md. Hasan Babu
2022	J	`jnl`	A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design. CoRR Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal
2022	J	`jnl`	BreastMultiNet: A multi-scale feature fusion method using deep neural network to detect breast cancer. Array Md. Mahbubur Rahman, Md. Saikat Islam Khan, Hafiz Md. Hasan Babu
2022	J	`jnl`	Chi Intell. Syst. Appl. Samrat Kumar Dey, Khandaker Mohammad Mohi Uddin, Hafiz Md. Hasan Babu, Md. Mahbubur Rahman, Arpita Howlader, K. M. Aslam Uddin
2022	J	`jnl`	DNA Technology for Multi-Valued Data Storage using Read Only Memory. FLAP Hafiz Md. Hasan Babu, Khandaker Mohammad Mohi Uddin, Tamanna Tabassum, Mohammed Nasir Uddin
2022	—	`conf`	Quantum Technology for Comparator Circuit. ISQED Hafiz Md. Hasan Babu, Khandaker Mohammad Mohi Uddin, Rownak Borhan Himel, Nitish Biswas
2018	J	`jnl`	A Fast FPGA-Based BCD Adder. Circuits Syst. Signal Process. Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu, Ashis Kumer Biswas
2017	—	`conf`	An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem. ISVLSI Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas
2017	—	`conf`	Area and Delay Efficient Design of a Quantum Bit String Comparator. ISVLSI Hafiz Md. Hasan Babu, Lafifa Jamal, Sayanton Vhaduri Dibbo, Ashis Kumer Biswas
2017	J	`jnl`	Cost-efficient design of a quantum multiplier-accumulator unit. Quantum Inf. Process. Hafiz Md. Hasan Babu
2017	J	`jnl`	Efficient Techniques for Fault Detection and Correction of Reversible Circuits. J. Electron. Test. Hafiz Md. Hasan Babu, Md. Solaiman Mia, Ashis Kumer Biswas
2017	J	`jnl`	Power efficient optimum design of the Reversible Plessey Logic Block of a field-programmable gate array. Sustain. Comput. Informatics Syst. Nazma Tara, Hafiz Md. Hasan Babu, Lafifa Jamal
2016	C	`conf`	A LUT-based matrix multiplication using neural networks. ISCAS Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu
2016	Misc	`conf`	An Improved Design of a Reversible Fault Tolerant LUT-based FPGA. VLSID Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu
2016	C	`conf`	An efficient design technique of a quantum divider circuit. ISCAS Sayanton Vhaduri Dibbo, Hafiz Md. Hasan Babu, Lafifa Jamal
2016	J	`jnl`	Design of a compact reversible fault tolerant division circuit. Microelectron. J. Hafiz Md. Hasan Babu, Md. Solaiman Mia
2016	C	`conf`	Design of an optimized reversible bidirectional barrel shifter. ISCAS Sadia Nowrin, Lafifa Jamal, Hafiz Md. Hasan Babu
2016	Misc	`conf`	Logic Synthesis in Reversible PLA. VLSID Nazma Tara, Hafiz Md. Hasan Babu, Nawshi Matin
2016	J	`jnl`	Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array. IET Circuits Devices Syst. Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md. Hasan Babu, Ashis Kumer Biswas
2015	C	`conf`	A compact representation of a quantum controlled ternary barrel shifter. ISCAS Nusrat Jahan Lisa, Hafiz Md. Hasan Babu
2015	—	`conf`	An Efficient Design of a Reversible Fault Tolerant n -to-2 ^n Sequence Counter Using Nano Meter MOS Transistors. ICSI (3) Md. Shamsujjoha, Sirin Nahar Sathi, Golam Sorwar, Fahmida Hossain, Md. Nawab Yousuf Ali, Hafiz Md. Hasan Babu
2015	—	`conf`	Design and Implementation of a Reversible Central Processing Unit. ISVLSI Lafifa Jamal, Hafiz Md. Hasan Babu
2015	Misc	`conf`	Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming. VLSID Nusrat Jahan Lisa, Hafiz Md. Hasan Babu
2015	—	`conf`	Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing. ISMVL Nusrat Jahan Lisa, Hafiz Md. Hasan Babu
2014	—	`conf`	A Cascading Wavelet-Feed Forward Neural Network Approach for Forecasting Traffic Flow. EDBT/ICDT Workshops Md. Mostafizur Rahman, Atsuhiro Takasu, Hafiz Md. Hasan Babu
2014	—	`conf`	A compact realization of an n-bit quantum carry skip adder circuit with optimal delay. AHS Nusrat Jahan Lisa, Hafiz Md. Hasan Babu
2014	C	`conf`	A novel approach to perform reversible addition/subtraction operations using deoxyribonucleic acid. ISCAS Ankur Sarker, Hafiz Md. Hasan Babu, Md. Saiful Islam
2014	J	`jnl`	Approach to design a compact reversible low power binary comparator. IET Comput. Digit. Tech. Hafiz Md. Hasan Babu, Nazir Saleheen, Lafifa Jamal, Sheikh Muhammad Sarwar, Tsutomu Sasao
2014	—	`conf`	Minimization of a reversible quantum 2 NANOARCH Nusrat Jahan Lisa, Hafiz Md. Hasan Babu
2013	Misc	`conf`	A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors. VLSI Design Md. Shamsujjoha, Hafiz Md. Hasan Babu
2013	—	`conf`	A novel approach to design a reversible shifter circuit using DNA. SoCC Tanvir Ahmed, Ankur Sarker, Mohd. Istiaq Sharif, S. M. Mahbubur Rashid, Md. Atiqur Rahman, Hafiz Md. Hasan Babu
2013	—	`conf`	An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder. SoCC Hafiz Md. Hasan Babu, Lafifa Jamal, Nazir Saleheen
2013	J	`jnl`	An efficient approach to design a reversible control unit of a processor. Sustain. Comput. Informatics Syst. Lafifa Jamal, Md. Masbaul Alam, Hafiz Md. Hasan Babu
2013	—	`conf`	An optimal design of a fault tolerant reversible multiplier. SoCC Lafifa Jamal, Md. Mushfiqur Rahman, Hafiz Md. Hasan Babu
2013	Misc	`conf`	Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter. VLSI Design Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal, Ahsan Raja Chowdhury
2013	J	`jnl`	Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis. Microelectron. J. Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal
2013	C	`conf`	Efficient approaches to design a reversible floating point divider. ISCAS Lafifa Jamal, Hafiz Md. Hasan Babu
2013	C	`conf`	Implementation of reversible multiplier circuit using Deoxyribonucleic acid. BIBE Ankur Sarker, Mohd. Istiaq Sharif, S. M. Mahbubur Rashid, Hafiz Md. Hasan Babu
2012	—	`conf`	An efficient approach for designing and minimizing reversible programmable logic arrays. ACM Great Lakes Symposium on VLSI Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, Hafiz Md. Hasan Babu
2012	—	`conf`	On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits. VDAT Lafifa Jamal, Md. Masbaul Alam Polash, M. A. Mottalib, Hafiz Md. Hasan Babu
2011	C	`conf`	Realization of Reversible Logic in DNA Computing. BIBE Ankur Sarker, Tanvir Ahmed, S. M. Mahbubur Rashid, Shahed Anwar, Lafifa Jamal, Nazma Tara, Md. Masbaul Alam, Hafiz Md. Hasan Babu
2010	Misc	`conf`	An Efficient Design of a Reversible Barrel Shifter. VLSI Design Irina Hashmi, Hafiz Md. Hasan Babu
2010	J	`jnl`	Building Toffoli Network for Reversible Logic Synthesis Based on Swapping Bit Strings CoRR Hafiz Md. Hasan Babu, Md. Saiful Islam, Md. Rafiqul Islam, Lafifa Jamal, Abu Ahmed Ferdaus, Muhammad Rezaul Karim, Abdullah Al Mahmud
2010	J	`jnl`	Efficient Wrapper/TAM Co-Optimization for SOC Using Rectangle Packing CoRR Md. Rafiqul Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Md. Saiful Islam, Hafiz Md. Hasan Babu
2010	J	`jnl`	Variable Block Carry Skip Logic using Reversible Gates CoRR Md. Rafiqul Islam, Md. Saiful Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Hafiz Md. Hasan Babu
2010	J	`jnl`	Wrapper/TAM Co-Optimization and Test Scheduling for SOCs Using Rectangle Bin Packing Considering Diagonal Length of Rectangles CoRR Md. Rafiqul Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Md. Saiful Islam, Hafiz Md. Hasan Babu
2010	J	`jnl`	Wrapper/TAM Co-Optimization and constrained Test Scheduling for SOCs Using Rectangle Bin Packing CoRR Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Md. Saiful Islam
2008	Misc	`conf`	A Novel Approach to Design BCD Adder and Carry Skip BCD Adder. VLSI Design Ashis Kumer Biswas, Md. Mahmudul Hasan, Moshaddek Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu
2008	J	`jnl`	Efficient approaches for designing reversible Binary Coded Decimal adders. Microelectron. J. Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu
2008	—	`conf`	Minimization of CTS of k-CNOT Circuits for SSF and MSF Model. DFT Muhammad Ibrahim, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu
2006	Misc	`conf`	A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array. VLSI Design Ahsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Hasan Babu
2006	J	`jnl`	Design of a compact reversible binary coded decimal adder circuit. J. Syst. Archit. Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
2006	—	`conf`	Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates. CDES Amin Ahsan Ali, Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
2005	C	`conf`	An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS. DSD Md. Sumon Shahriar, A. R. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, Hafiz Md. Hasan Babu
2005	Misc	`conf`	Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder. VLSI Design Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
2004	—	`conf`	A heuristic approach to synthesize Boolean functions using TANT network. ISCAS (2) Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Haque, Ahsan Raja Chowdhury
2004	C	`conf`	Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic. DSD Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam
2004	—	`conf`	On the Minimization of Multiple-Valued Input Binary-Valued Output Functions. ISMVL Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Rafiqul Islam, Md. Mazder Rahman
2004	Misc	`conf`	Synthesis of Full-Adder Circuit Using Reversible Logic. VLSI Design Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury
2003	—	`conf`	A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic. Asian Test Symposium Md. Rafiqul Islam, Hafiz Md. Hasan Babu, Mohammad Abdur Rahim Mustafa, Md. Sumon Shahriar
2003	—	`conf`	A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits. ISMVL Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Amin Ahsan Ali, Mohammad Musa Salehin Akon
2003	C	`conf`	Reversible Logic Synthesis for Minimization of Full-Adder Circuit. DSD Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury
2000	—	`conf`	Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. ISMVL Hafiz Md. Hasan Babu, Tsutomu Sasao
1999	—	`conf`	Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions. ISMVL Hafiz Md. Hasan Babu, Tsutomu Sasao
1998	—	`conf`	Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams. ISMVL Hafiz Md. Hasan Babu, Tsutomu Sasao