Hae-Seung Lee - RankMe

93 papers A* 1A 1C 6Journal 50Unranked 35

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	Mitigation of Vertical Fixed Pattern Noise in CMOS Image Sensors through Analog Offset Dithering and Dynamic Clock Adjustment. ISCAS Jaejin Jung, Sungyong Kim, Shinhwan Lim, Kyoungmin Koh, Hae-Seung Lee
2025	J	`jnl`	Protecting the Mixed-Signal Domain: Secure ADCs for Internet of Things Devices. Proc. IEEE Maitreyi Ashok, Ruicong Chen, Taehoon Jeong, Anantha P. Chandrakasan, Hae-Seung Lee
2024	J	`jnl`	A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. IEEE J. Solid State Circuits Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
2024	J	`jnl`	Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design. CoRR Tanner Andrulis, Ruicong Chen, Hae-Seung Lee, Joel S. Emer, Vivienne Sze
2023	—	`conf`	A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. VLSI Technology and Circuits Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
2023	—	`conf`	Machine Learning for Arterial Blood Pressure Prediction. CHIL Jessica Zheng, Hanrui Wang, Anand Chandrasekhar, Aaron D. Aguirre, Song Han, Hae-Seung Lee, Charles G. Sodini
2023	—	`conf`	Sniff-SAR: A 9.8fJ/c.-s 12b secure ADC with detectiondriven protection against power and EM side-channel attack. CICC Ruicong Chen, Anantha P. Chandrakasan, Hae-Seung Lee
2022	A	`conf`	A Bit-level Sparsity-aware SAR ADC with Direct Hybrid Encoding for Signed Expressions for AIoT Applications. ISLPED Ruicong Chen, H. T. Kung, Anantha P. Chandrakasan, Hae-Seung Lee
2022	—	`conf`	RaM-SAR: A Low Energy and Area Overhead, 11.3fJ/conv.-step 12b 25MS/s Secure Random-Mapping SAR ADC with Power and EM Side-channel Attack Resilience. VLSI Technology and Circuits Ruicong Chen, Hanrui Wang, Anantha P. Chandrakasan, Hae-Seung Lee
2021	J	`jnl`	Non-Invasive Evaluation of a Carotid Arterial Pressure Waveform Using Motion-Tolerant Ultrasound Measurements During the Valsalva Maneuver. IEEE J. Biomed. Health Informatics Joohyun Seo, Hae-Seung Lee, Charles G. Sodini
2021	J	`jnl`	S2ADC: A 12-bit, 1.25-MS/s Secure SAR ADC With Power Side-Channel Attack Resistance. IEEE J. Solid State Circuits Taehoon Jeong, Anantha P. Chandrakasan, Hae-Seung Lee
2020	A*	`conf`	GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. DAC Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han
2020	J	`jnl`	GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. CoRR Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han
2020	—	`conf`	S2ADC: A 12-bit, 1.25MS/s Secure SAR ADC with Power Side-Channel Attack Resistance. CICC Taehoon Jeong, Anantha P. Chandrakasan, Hae-Seung Lee
2019	—	`conf`	An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS. ESSCIRC Xi Yang, Seung-Jun Bae, Hae-Seung Lee
2018	C	`conf`	Design of a 6 ISCAS Xi Yang, Hae-Seung Lee
2018	—	`conf`	EMG-based Real Time Facial Gesture Recognition for Stress Monitoring. EMBC Sirma Orguc, Harneet Singh Khurana, Konstantina M. Stankovic, Hae-Seung Lee, Anantha P. Chandrakasan
2018	J	`jnl`	Learning to Design Circuits. CoRR Hanrui Wang, Jiacheng Yang, Hae-Seung Lee, Song Han
2018	—	`conf`	Monitoring of Pulse Pressure and Arterial Pressure Waveform Changes during the Valsalva Maneuver by a Portable Ultrasound System. EMBC Joohyun Seo, Charles G. Sodini, Hae-Seung Lee
2018	C	`conf`	Recode then LSB-first SAR ADC for Reducing Energy and Bit-cycles. ISCAS Harneet Singh Khurana, Anantha P. Chandrakasan, Hae-Seung Lee
2017	—	`conf`	0.3 V ultra-low power sensor interface for EMG. ESSCIRC Sirma Orguc, Harneet Singh Khurana, Hae-Seung Lee, Anantha P. Chandrakasan
2016	J	`jnl`	A Column-Row-Parallel ASIC Architecture for 3-D Portable Medical Ultrasonic Imaging. IEEE J. Solid State Circuits Kailiang Chen, Hae-Seung Lee, Charles G. Sodini
2016	—	`conf`	A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCs. ACM Great Lakes Symposium on VLSI Daniel Prashanth, Hae-Seung Lee
2016	—	`conf`	Data converter reflections: 19 papers from the last ten years that deserve a second look. ESSCIRC David Robertson, Aaron Buchwald, Michael Flynn, Hae-Seung Lee, Un-Ku Moon, Boris Murmann
2016	C	`conf`	Design of a 4th-order multi-stage feedforward operational amplifier for continuous-time bandpass delta sigma modulators. ISCAS Xi Yang, Hae-Seung Lee
2015	—	`conf`	15.1 An 85dB-DR 74.6dB-SNDR 50MHZ-BW CT MASH ΔΣ modulator in 28nm CMOS. ISSCC Do-Yeon Yoon, Stacy Ho, Hae-Seung Lee
2015	—	`conf`	15.6 12b 250MS/S pipelined ADC with virtual ground reference buffers. ISSCC Hyun Ho Boo, Duane S. Boning, Hae-Seung Lee
2015	J	`jnl`	A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers. IEEE J. Solid State Circuits Hyun Ho Boo, Duane S. Boning, Hae-Seung Lee
2015	—	`conf`	A 200-MS/s 98-dB SNR track-and-hold in 0.25-um GaN HEMT. CICC SungWon Chung, Hae-Seung Lee
2015	J	`jnl`	A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28 nm CMOS. IEEE J. Solid State Circuits Do-Yeon Yoon, Stacy Ho, Hae-Seung Lee
2015	—	`conf`	Carotid arterial blood pressure waveform monitoring using a portable ultrasound system. EMBC Joohyun Seo, Sabino J. Pietrangelo, Hae-Seung Lee, Charles G. Sodini
2015	—	`conf`	Session 26 overview: Nyquist-rate converters: Data converters subcommittee. ISSCC Hae-Seung Lee, Seng-Pan Li
2014	—	`conf`	11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR. ISSCC Dong-Young Chang, Carlos E. Muñoz, Denis C. Daly, Soon-Kyun Shin, Kevin Guay, Thomas Thurston, Hae-Seung Lee, Kush Gulati, Matthew Z. Straayer
2014	—	`conf`	22.4 A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration. ISSCC Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee
2014	J	`jnl`	A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration. IEEE J. Solid State Circuits Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee
2014	J	`jnl`	A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration. IEEE J. Solid State Circuits Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer
2014	—	`conf`	A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging. VLSIC Kailiang Chen, Hae-Seung Lee, Charles G. Sodini
2013	—	`conf`	A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration. ESSCIRC Albert H. Chang, Hae-Seung Lee, Duane S. Boning
2013	—	`conf`	Power-efficient amplifier frequency compensation for continuous-time delta-sigma modulators. MWSCAS Do-Yeon Yoon, Hae-Seung Lee, Jeffrey Gealow
2013	J	`jnl`	Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver. IEEE J. Solid State Circuits Kailiang Chen, Hae-Seung Lee, Anantha P. Chandrakasan, Charles G. Sodini
2012	J	`jnl`	A 12 b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC. IEEE J. Solid State Circuits Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee
2012	—	`conf`	A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS. CICC Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer
2012	—	`conf`	A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration. ESSCIRC Nan Sun, Hae-Seung Lee, Donhee Ham
2011	—	`conf`	A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC. ESSCIRC Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee
2011	—	`conf`	A 450 MS/s 10-bit time-interleaved zero-crossing based ADC. CICC Jack Chu, Hae-Seung Lee
2011	—	`conf`	Redundancy in SAR ADCs. ACM Great Lakes Symposium on VLSI Albert H. Chang, Hae-Seung Lee, Duane S. Boning
2011	J	`jnl`	Zero-Crossing Detector Based Reconfigurable Analog System. IEEE J. Solid State Circuits Payam Lajevardi, Anantha P. Chandrakasan, Hae-Seung Lee
2010	C	`conf`	Offset cancellation for zero crossing based circuits. ISCAS Albert Chow, Hae-Seung Lee
2010	J	`jnl`	Zero-Crossing-Based Ultra-Low-Power A/D Converters. Proc. IEEE Hae-Seung Lee, Lane Brooks, Charles G. Sodini
2009	—	`conf`	A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB. ISSCC Lane Brooks, Hae-Seung Lee
2009	J	`jnl`	A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC. IEEE J. Solid State Circuits Lane Brooks, Hae-Seung Lee
2009	J	`jnl`	Noise Analysis for Comparator-Based Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Todd Sepke, Peter Holloway, Charles G. Sodini, Hae-Seung Lee
2008	—	`conf`	A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control. CICC Moo-Yeol Choi, Sung-No Lee, Seung-Bin You, Wang-Seup Yeum, Ho-Jin Park, Jae-Whui Kim, Hae-Seung Lee
2008	—	`conf`	A 16b 10MS/s digitally self-calibrated ADC with time constant control. CICC Tae-Hwan Oh, Ho-Young Lee, Ju-Hwa Kim, Ho-Jin Park, Kyoung-Ho Moon, Jae-Whui Kim, Hae-Seung Lee
2008	J	`jnl`	Analog-to-Digital Converters: Digitizing the Analog World. Proc. IEEE Hae-Seung Lee, Charles G. Sodini
2008	J	`jnl`	Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation. IEEE Trans. Circuits Syst. I Regul. Pap. Lane Brooks, Hae-Seung Lee
2008	J	`jnl`	Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching. IEEE Trans. Circuits Syst. II Express Briefs Nan Sun, Hae-Seung Lee, Donhee Ham
2007	—	`conf`	A 14-b 30MS/s 0.75mm CICC Ho-Young Lee, Tae-Hwan Oh, Ho-Jin Park, Hae-Seung Lee, Mark Spaeth, Jae-Whui Kim
2007	J	`jnl`	A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC. IEEE J. Solid State Circuits Lane Brooks, Hae-Seung Lee
2007	—	`conf`	A Zero-Crossing-Based 8b 200MS/s Pipelined ADC. ISSCC Lane Brooks, Hae-Seung Lee
2007	C	`conf`	Transient Noise Analysis for Comparator-Based Switched-Capacitor Circuits. ISCAS Albert Chow, Hae-Seung Lee
2006	—	`conf`	A 3MPixel Low-Noise Flexible Architecture CMOS Image Sensor. ISSCC Jungwook Yang, Keith Fife, Lane Brooks, Charles G. Sodini, Andrew Betts, Pavan Mudunuru, Hae-Seung Lee
2006	J	`jnl`	Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies. IEEE J. Solid State Circuits John Kenneth Fiorenza, Todd Sepke, Peter Holloway, Charles G. Sodini, Hae-Seung Lee
2006	—	`conf`	Comparator-based switched-capacitor circuits for scaled CMOS technologies. ISSCC Todd Sepke, John Kenneth Fiorenza, Charles G. Sodini, Peter Holloway, Hae-Seung Lee
2005	J	`jnl`	CMOS-based microdisplay with calibrated backplane. IEEE J. Solid State Circuits Andrew R. Chen, Akintunde Ibitayo (Tayo) Akinwande, Hae-Seung Lee
2004	J	`jnl`	Radio frequency digital-to-analog converter. IEEE J. Solid State Circuits Susan Luschas, Richard Schreier, Hae-Seung Lee
2004	J	`jnl`	Study of substrate noise and techniques for minimization. IEEE J. Solid State Circuits Mark Shane Peng, Hae-Seung Lee
2003	—	`conf`	A 942 MHz output, 17.5 MHz bandwidth, -70dBc IMD3 ΣΔ DAC. CICC Susan Luschas, Richard Schreier, Hae-Seung Lee
2003	—	`conf`	Output impedance requirements for DACs. ISCAS (1) Susan Luschas, Hae-Seung Lee
2002	J	`jnl`	Oversampled pipeline A/D converters with mismatch shaping. IEEE J. Solid State Circuits Ayman Shabra, Hae-Seung Lee
2002	J	`jnl`	Superconducting bandpass ΔΣ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate. IEEE J. Solid State Circuits John F. Bulzacchelli, Hae-Seung Lee, James A. Misewich, Mark B. Ketchen
2001	J	`jnl`	A low-power reconfigurable analog-to-digital converter. IEEE J. Solid State Circuits Kush Gulati, Hae-Seung Lee
2000	J	`jnl`	Corrections to "a high-swing CMOS telescopic operational amplifier". IEEE J. Solid State Circuits Kush Gulati, Hae-Seung Lee
1999	J	`jnl`	A Nyquist-rate pipelined oversampling A/D converter. IEEE J. Solid State Circuits Susanne A. Paul, Hae-Seung Lee, John Goodrich, Titiimaea F. Alailima, Daniel D. Santiago
1998	J	`jnl`	A high-swing CMOS telescopic operational amplifier. IEEE J. Solid State Circuits Kush Gulati, Hae-Seung Lee
1998	J	`jnl`	A mixed-signal array processor with early vision applications. IEEE J. Solid State Circuits David A. Martin, Hae-Seung Lee, Ichiro Masaki
1998	J	`jnl`	Estimating the Focus of Expansion in Analog VLSI. Int. J. Comput. Vis. Ignacio S. McQuirk, Berthold K. P. Horn, Hae-Seung Lee, John L. Wyatt Jr.
1996	J	`jnl`	A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC. IEEE J. Solid State Circuits Paul C. Yu, Hae-Seung Lee
1996	J	`jnl`	A 9-b charge-to-digital converter for integrated image sensors. IEEE J. Solid State Circuits Susanne A. Paul, Hae-Seung Lee
1994	J	`jnl`	16-channel oversampled analog-to-digital converter. IEEE J. Solid State Circuits S. Nadeem, Charles G. Sodini, Hae-Seung Lee
1994	J	`jnl`	A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC. IEEE J. Solid State Circuits Hae-Seung Lee
1994	J	`jnl`	A 300-MHz BiCMOS serial data transceiver. IEEE J. Solid State Circuits Barry Thompson, Hae-Seung Lee, Lawrence M. DeVito
1994	J	`jnl`	Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs. IEEE J. Solid State Circuits Theodore L. Tewksbury, Hae-Seung Lee
1993	J	`jnl`	A 15-b 1-Msample/s digitally self-calibrated pipeline ADC. IEEE J. Solid State Circuits Andrew N. Karanicolas, Hae-Seung Lee, Kantilal L. Barcrania
1993	J	`jnl`	A 40*40 CCD/CMOS absolute-value-of-difference processor for use in a stereo vision system. IEEE J. Solid State Circuits J. Mikko Hakkarainen, Hae-Seung Lee
1993	J	`jnl`	A high-swing 2-V CMOS operational amplifier with replica-amp gain enhancement. IEEE J. Solid State Circuits Paul C. Yu, Hae-Seung Lee
1992	J	`jnl`	Analog VLSI systems for image acquisition and fast early vision processing. Int. J. Comput. Vis. John L. Wyatt Jr., Craig L. Keast, Mark Seidel, David L. Standley, Berthold K. P. Horn, Tom Knight, Charles G. Sodini, Hae-Seung Lee, Tomaso A. Poggio
1992	J	`jnl`	CMOS resistive fuses for image smoothing and segmentation. IEEE J. Solid State Circuits Paul C. Yu, Steven J. Decker, Hae-Seung Lee, Charles G. Sodini, John L. Wyatt Jr.
1991	J	`jnl`	A high-frequency fully differential BiCMOS operational amplifier. IEEE J. Solid State Circuits Andrew N. Karanicolas, Kenneth K. O, John Y. A. Wang, Hae-Seung Lee, Rafael L. Reif
1989	J	`jnl`	A 200-MHz CMOS phase-locked loop with dual phase detectors. IEEE J. Solid State Circuits Kurt M. Ware, Hae-Seung Lee, Charles G. Sodini
1989	J	`jnl`	The effects of oxide traps on the large-signal transient response of analog MOS circuits. IEEE J. Solid State Circuits Theodore L. Tewksbury, Hae-Seung Lee, Gerald A. Miller
1988	J	`jnl`	A digital readout technique for capacitive sensor applications. IEEE J. Solid State Circuits Joseph T. Kung, Hae-Seung Lee, Roger T. Howe
1988	J	`jnl`	A high-speed CMOS comparator for use in an ADC. IEEE J. Solid State Circuits Benjamin J. McCarroll, Charles G. Sodini, Hae-Seung Lee