Hadi Parandeh-Afshar

29 papers A* 1A 10B 5C 1Misc 1Journal 5Unranked 5

Year	Rank	Type	Title / Venue / Authors
2018	A	`conf`	Approximate quaternary addition with the fast carry chains of FPGAs. DATE Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk
2018	—	`conf`	Exploration of approximate multipliers design space using carry propagation free compressors. ASP-DAC Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi
2017	—	`conf`	CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design. DFT Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi
2014	A	`conf`	Revisiting and-inverter cones. FPGA Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne
2013	A	`conf`	Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
2013	B	`conf`	Shadow And-Inverter Cones. FPL Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
2012	—	`—`	Closing the Gap between FPGA and ASIC - Balancing Flexibility and Efficiency. Hadi Parandeh-Afshar
2012	A	`conf`	Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk
2012	A	`conf`	Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. FPGA Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne
2011	J	`jnl`	Compressor tree synthesis on commercial high-performance FPGAs. ACM Trans. Reconfigurable Technol. Syst. Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne
2011	B	`conf`	Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. FPL Hadi Parandeh-Afshar, Paolo Ienne
2011	A	`conf`	Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne
2010	Misc	`conf`	Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. FCCM Hadi Parandeh-Afshar, Paolo Ienne
2010	J	`jnl`	Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2010	B	`conf`	Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2009	A	`conf`	3D configuration caching for 2D FPGAs. FPGA Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj
2009	—	`conf`	A flexible DSP block to enhance FPGA arithmetic performance. FPT Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	J	`jnl`	An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. ACM Trans. Reconfigurable Technol. Syst. Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2009	B	`conf`	Exploiting fast carry-chains of FPGAs for designing compressor trees. FPL Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2009	J	`jnl`	Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	B	`conf`	Using 3D integration technology to realize multi-context FPGAs. FPL Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2008	A	`conf`	A novel FPGA logic block for improved arithmetic performance. FPGA Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2008	A	`conf`	Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
2008	—	`conf`	Efficient synthesis of compressor trees on FPGAs. ASP-DAC Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2008	A	`conf`	Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2007	A*	`conf`	Enhancing FPGA Performance for Arithmetic Circuits. DAC Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar
2007	J	`jnl`	Fast INC-XOR codec for low-power address buses. IET Comput. Digit. Tech. Hadi Parandeh-Afshar, Mohsen Saneei, Ali Afzali-Kusha, Massoud Pedram
2006	—	`conf`	A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor. ICECS Hadi Parandeh-Afshar, Mohsen Ahmadvand, Saeed Safari
2006	C	`conf`	A very high performance address BUS encoder. ISCAS Hadi Parandeh-Afshar, Ali Afzali-Kusha, Ali Khaki-Firooz