H. Udayakumar - RankMe

13 papers A 1C 1Misc 6Unranked 5

Year	Rank	Type	Title / Venue / Authors
2009	Misc	`conf`	An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. VLSI Design Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind
2009	—	`conf`	Clock gating effectiveness metrics: Applications to power optimization. ISQED Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao
2009	—	`conf`	Optimization strategies to improve statistical timing. ISQED Parimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar
2008	—	`conf`	An SSO Based Methodology for EM Emission Estimation from SoCs. ISQED Sukumar Jairam, S. M. Stalin, Jean-Yves Oberle, H. Udayakumar
2008	A	`conf`	Clock gating for power optimization in ASIC design cycle theory & practice. ISLPED Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao
2008	—	`conf`	Memory Power Modeling - A Novel Approach. ISVLSI Ajit Gupte, Mohit Sharma, Gaurav Varshney, Lakshmikantha Holla, Parvinder Rana, H. Udayakumar
2006	Misc	`conf`	A Methodology for Switching Activity Based IO Powerpad Optimisation. VLSI Design Snehashis Roy, Sukumar Jairam, H. Udayakumar
2005	Misc	`conf`	A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses. VLSI Design Sankar P. Debnath, Sukumar Jairam, H. Udayakumar
2004	Misc	`conf`	Package-silicon co-design - Experiment with an SOC design. VLSI Design P. R. Suresh, P. K. Sundararajan, Anshuli Goel, H. Udayakumar, C. Srinivasan, Vasudev Sinari, Raghavendrakumar Ravinutala
2002	—	`conf`	Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. ASP-DAC/VLSI Design Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji
2000	Misc	`conf`	A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. VLSI Design Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar
1999	C	`conf`	A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. ICCD Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G.
1999	Misc	`conf`	A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. VLSI Design Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar