H. Peter Hofstee

103 papers A* 4A 4B 5C 5Misc 5Journal 48Unranked 28

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	GenMPI: Cluster Scalable Variant Calling for Short/Long Reads Sequencing Data. IEEE Trans. Comput. Biol. Bioinform. Tanveer Ahmad, Joseph Schuchart, Zaid Al-Ars, Christoph Niethammer, José Gracia, H. Peter Hofstee
2025	J	`jnl`	Low-Loss Space in Neural Networks is Continuous and Fully Connected. CoRR Yongding Tian, Zaid Al-Ars, Maksim Kitsak, H. Peter Hofstee
2025	Misc	`conf`	Open-Vocabulary Object Detection with Driving-Aware Multi-Scale Feature Fusion for Autonomous Driving. SEC Tianyang Chen, Yongtao Yao, H. Peter Hofstee, Weisong Shi
2024	J	`jnl`	Hardware-Accelerator Design by Composition: Dataflow Component Interfaces With Tydi-Chisel. IEEE Trans. Very Large Scale Integr. Syst. Casper Cromjongh, Yongding Tian, H. Peter Hofstee, Zaid Al-Ars
2024	—	`conf`	Learning Structured Sparsity for Efficient Nanopore DNA Basecalling Using Delayed Masking. BCB Mees Frensel, Zaid Al-Ars, H. Peter Hofstee
2024	J	`jnl`	Leveraging Apache Arrow for Zero-copy, Zero-serialization Cluster Shared Memory. CoRR Philip Groet, Joost Hoozemans, Andreas Grapentin, Felix Eberhardt, Zaid Al-Ars, H. Peter Hofstee
2024	—	`conf`	Tywaves: A Typed Waveform Viewer for Chisel. NorCAS Raffaele Meloni, H. Peter Hofstee, Zaid Al-Ars
2024	J	`jnl`	Tywaves: A Typed Waveform Viewer for Chisel. CoRR Raffaele Meloni, H. Peter Hofstee, Zaid Al-Ars
2024	J	`jnl`	Vanishing Variance Problem in Fully Decentralized Neural-Network Systems. CoRR Yongding Tian, Zaid Al-Ars, Maksim Kitsak, H. Peter Hofstee
2023	—	`conf`	An Intermediate Representation for Composable Typed Streaming Dataflow Designs. VLDB Workshops Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten
2023	J	`jnl`	An Intermediate Representation for Composable Typed Streaming Dataflow Designs. CoRR Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten
2023	—	`conf`	OctoRay: Framework for Scalable FPGA Cluster Acceleration of Python Big Data Applications. SC Workshops Zaid Al-Ars, Jakoba Petri-Koenig, Joost Hoozemans, Luc Dierick, H. Peter Hofstee
2023	J	`jnl`	SaLoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs. CoRR Seongyeon Park, Hajin Kim, Tanveer Ahmad, Nauman Ahmed, Zaid Al-Ars, H. Peter Hofstee, Youngsok Kim, Jinho Lee
2023	—	`conf`	Tydi-Chisel: Collaborative and Interface-Driven Data-Streaming Accelerators. NorCAS Casper Cromjongh, Yongding Tian, H. Peter Hofstee, Zaid Al-Ars
2023	—	`conf`	Tydi-lang: A Language for Typed Streaming Hardware. SC Workshops Yongding Tian, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten
2022	J	`jnl`	A Toolchain for Streaming Dataflow Accelerator Designs for Big Data Analytics: Defining an IR for Composable Typed Streaming Dataflow Designs. CoRR Matthijs A. Reukers, H. Peter Hofstee, Zaid Al-Ars
2022	J	`jnl`	Benchmarking Apache Arrow Flight - A wire-speed protocol for data transfer, querying and microservices. CoRR Tanveer Ahmad, Zaid Al-Ars, H. Peter Hofstee
2022	C	`conf`	Communication-Efficient Cluster Scalable Genomics Data Processing Using Apache Arrow Flight. ISPDC Tanveer Ahmad, Chengxin Ma, Zaid Al-Ars, H. Peter Hofstee
2022	A	`conf`	Improving Gradient Paths for Binary Convolutional Neural Networks. BMVC Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars
2022	A	`conf`	SALoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs. IPDPS Seongyeon Park, Hajin Kim, Tanveer Ahmad, Nauman Ahmed, Zaid Al-Ars, H. Peter Hofstee, Youngsok Kim, Jinho Lee
2022	J	`jnl`	The Future of FPGA Acceleration in Datacenters and the Cloud. ACM Trans. Reconfigurable Technol. Syst. Christophe Bobda, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin C. Herbordt, Hafsah Shahzad, H. Peter Hofstee, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, Russell Tessier
2022	J	`jnl`	Tydi-lang: A Language for Typed Streaming Hardware. CoRR Yongding Tian, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten
2022	J	`jnl`	Tydi-lang: a language for typed streaming hardware - A manual for future Tydi-lang compiler developers. CoRR Yongding Tian, Zaid Al-Ars, H. Peter Hofstee
2021	—	`conf`	An Attention Module for Convolutional Neural Networks. ICANN (1) Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars
2021	J	`jnl`	An Attention Module for Convolutional Neural Networks. CoRR Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars
2021	A*	`conf`	AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression. IJCAI Baozhou Zhu, H. Peter Hofstee, Johan Peltenburg, Jinho Lee, Zaid Al-Ars
2021	J	`jnl`	AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression. CoRR Baozhou Zhu, H. Peter Hofstee, Johan Peltenburg, Jinho Lee, Zaid Al-Ars
2021	J	`jnl`	Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow. J. Signal Process. Syst. Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee
2021	J	`jnl`	Low Latency and High Throughput Write-Ahead Logging Using CAPI-Flash. IEEE Trans. Cloud Comput. Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee
2020	J	`jnl`	An Efficient High-Throughput LZ77-Based Decompressor in Reconfigurable Logic. J. Signal Process. Syst. Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee
2020	—	`conf`	Battling the CPU Bottleneck in Apache Parquet to Arrow Conversion Using FPGA. FPT Johan Peltenburg, Lars T. J. van Leeuwen, Joost Hoozemans, Jian Fang, Zaid Al-Ars, H. Peter Hofstee
2020	A	`ed.`	ICS '20: 2020 International Conference on Supercomputing, Barcelona Spain, June, 2020 ICS Eduard Ayguadé, Wen-mei W. Hwu, Rosa M. Badia, H. Peter Hofstee
2020	J	`jnl`	In-memory database acceleration on FPGAs: a survey. VLDB J. Jian Fang, Yvo T. B. Mulder, Jan Hidders, Jinho Lee, H. Peter Hofstee
2020	B	`conf`	NASB: Neural Architecture Search for Binary Convolutional Neural Networks. IJCNN Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee
2020	J	`jnl`	NASB: Neural Architecture Search for Binary Convolutional Neural Networks. CoRR Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee
2020	J	`jnl`	Optimizing performance of GATK workflows using Apache Arrow In-Memory data framework. BMC Genom. Tanveer Ahmad, Nauman Ahmed, Zaid Al-Ars, H. Peter Hofstee
2020	J	`jnl`	REAF: Reducing Approximation of Channels by Reducing Feature Reuse Within Convolution. IEEE Access Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee
2020	J	`jnl`	SoFAr: Shortcut-based Fractal Architectures for Binary Convolutional Neural Networks. CoRR Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars
2020	A*	`conf`	ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation. MICRO Christian Pinto, Dimitris Syrivelis, Michele Gazzetti, Panos K. Koutsovasilis, Andrea Reale, Kostas Katrinis, H. Peter Hofstee
2020	J	`jnl`	Tydi: An Open Specification for Complex Data Structures Over Hardware Streams. IEEE Micro Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee
2019	Misc	`conf`	A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model. FCCM Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee
2019	B	`conf`	Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow. FPL Johan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars van Leeuwen, Zaid Al-Ars, H. Peter Hofstee
2019	—	`conf`	Refine and Recycle: A Method to Increase Decompression Parallelism. ASAP Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee
2019	—	`conf`	Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow. ARC Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars
2019	—	`conf`	Video-Text Compliance: Activity Verification Based on Natural Language Instructions. ICCV Workshops Mayoore Jaiswal, H. Peter Hofstee, Valerie Chen, Suvadip Paul, Rogério Feris, Frank Liu, Anupama Jagannathan, Anne Gattiker, Inseok Hwang, Jinho Lee, Matthew Tong, Sahil Dureja, Soham Shah
2018	—	`conf`	A 64-GB Sort at 28 GB/s on a 4-GPU POWER9 Node for Uniformly-Distributed 16-Byte Records with 8-Byte Keys. ISC Workshops Gordon C. Fossum, Ting Wang, H. Peter Hofstee
2018	J	`jnl`	A hardware compilation framework for text analytics queries. J. Parallel Distributed Comput. Raphael Polig, Kubilay Atasu, Heiner Giefers, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee
2018	Misc	`conf`	A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress. CODES+ISSS Jian Fang, Jianyu Chen, Zaid Al-Ars, H. Peter Hofstee, Jan Hidders
2018	—	`conf`	CAPI-Flash Accelerated Persistent Read Cache for Apache Cassandra. IEEE CLOUD Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee
2018	J	`jnl`	Giving Text Analytics a Boost. CoRR Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Eva Sitaridi, Huaiyu Zhu
2017	—	`conf`	Analyzing In-Memory Hash Join: Granularity Matters. ADMS@VLDB Jian Fang, Jinho Lee, H. Peter Hofstee, Jan Hidders
2017	J	`jnl`	ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator. Proc. VLDB Endow. Jinho Lee, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi-Joon Nam, Mark Nutter, Damir A. Jamsek
2017	—	`conf`	SparkGA: A Spark Framework for Cost Effective, Fast and Accurate DNA Analysis at Scale. BCB Hamid Mushtaq, Frank Liu, Carlos Costa, Gang Liu, H. Peter Hofstee, Zaid Al-Ars
2016	B	`conf`	Auto-tuning Spark Big Data Workloads on POWER8: Prediction-Based Dynamic SMT Threading. PACT Zhen Jia, Chao Xue, Guancheng Chen, Jianfeng Zhan, Lixin Zhang, Yonghua Lin, H. Peter Hofstee
2016	B	`conf`	Optimized Durable Commitlog for Apache Cassandra Using CAPI-Flash. CLOUD Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee
2016	J	`jnl`	PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor. IEEE Comput. Archit. Lett. Minghua Li, Guancheng Chen, Qijun Wang, Yonghua Lin, H. Peter Hofstee, Per Stenström, Dian Zhou
2016	—	`conf`	RAW 2016 Keynotes. IPDPS Workshops H. Peter Hofstee, Patrick Lysaght, Dirk van den Heuvel
2015	J	`jnl`	Feature detection for image analytics via FPGA acceleration. IBM J. Res. Dev. Hua-Yu Chang, Iris Hui-Ru Jiang, H. Peter Hofstee, Damir A. Jamsek, Gi-Joon Nam
2015	J	`jnl`	Second-Generation Big Data Systems. Computer Fadi H. Gebara, H. Peter Hofstee, Kevin J. Nowka
2014	J	`jnl`	Giving Text Analytics a Boost. IEEE Micro Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Huaiyu Zhu, Eva Sitaridi
2014	—	`conf`	Hardware-accelerated text analytics. Hot Chips Symposium Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee
2013	J	`jnl`	Big Data text-oriented benchmark creation for Hadoop. IBM J. Res. Dev. Anne E. Gattiker, Fadi H. Gebara, H. Peter Hofstee, J. D. Hayes, A. Hylick
2013	J	`jnl`	True hardware random number generation implemented in the 32-nm SOI POWER7+ processor. IBM J. Res. Dev. John S. Liberty, Adrian Barrera, David W. Boerstler, Thomas B. Chadwick, Scott R. Cottier, H. Peter Hofstee, Julie A. Rosser, Marty L. Tsai
2013	J	`jnl`	Understanding system design for Big Data workloads. IBM J. Res. Dev. H. Peter Hofstee, Guan-Cheng Chen, Fadi H. Gebara, Kevin Hall, Jay Herring, Damir A. Jamsek, Jian Li, Yan Li, Juwei Shi, Peter Wai Yee Wong
2011	—	`ch.`	Cell Broadband Engine Processor. Encyclopedia of Parallel Computing H. Peter Hofstee
2009	—	`conf`	HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? Euro-Par Workshops Martti Forsell, H. Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff
2009	—	`ch.`	Heterogeneous Multi-core Processors: The Cell Broadband Engine. Multicore Processors and Systems H. Peter Hofstee
2009	—	`book`	Multicore Processors and Systems Stephen W. Keckler, Kunle Olukotun, H. Peter Hofstee
2009	—	`conf`	The Next 25 Years of Computer Architecture? Euro-Par Workshops H. Peter Hofstee
2008	—	`conf`	Rome Reborn. SIGGRAPH New Tech Demos Bernard D. Frischer, Dean Abernathy, Gabriele Guidi, Joel Myers, Cassie Thibodeau, Antonio Salvemini, Pascal Müller, H. Peter Hofstee, Barry Minor
2007	—	`conf`	Cell Broadband Engine Processor Design Methodology. CICC Osamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, C. J. Johnson, Stephen D. Posluszny
2007	J	`jnl`	Cell Broadband Engine processor vault security architecture. IBM J. Res. Dev. Kanna Shimizu, H. Peter Hofstee, John S. Liberty
2007	J	`jnl`	Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata
2007	J	`jnl`	Preface. IBM J. Res. Dev. H. Peter Hofstee, Ashwini K. Nanda, John J. Ritsko
2007	C	`conf`	The future of multi-core technologies. CLUSTER Michael T. Clark, H. Peter Hofstee, Edward J. Barragy, Ian Buck, Stephen W. Keckler
2006	A	`conf`	Invited speakers II - Real-time supercomputing and technology for games and entertainment. SC H. Peter Hofstee
2006	—	`conf`	Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. ASP-DAC Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel
2006	J	`jnl`	Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. IEEE J. Solid State Circuits Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa
2006	J	`jnl`	Synergistic Processing in Cell's Multicore Architecture. IEEE Micro Michael Gschwind, H. Peter Hofstee, Brian K. Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki
2006	J	`jnl`	The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid State Circuits Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata
2005	—	`conf`	Communication and Synchronization in the Cell Processor - Invited Talk. CPA H. Peter Hofstee
2005	Misc	`conf`	Hardware and software architectures for the CELL processor. CODES+ISSS H. Peter Hofstee, Michael N. Day
2005	J	`jnl`	Introduction to the Cell multiprocessor. IBM J. Res. Dev. James A. Kahle, Michael N. Day, H. Peter Hofstee, Charles R. Johns, Theodore R. Maeurer, David J. Shippy
2005	A*	`conf`	Power Efficient Processor Architecture and The Cell Processor. HPCA H. Peter Hofstee
2005	—	`conf`	The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. CICC Dac C. Pham, Erwin Behnen, Mark Bolliger, H. Peter Hofstee, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Yoshio Masubuchi, Stephen D. Posluszny, Mack W. Riley, Masakazu Suzuoki, Michael Wang, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Kazuaki Yazawa
2002	C	`conf`	Power-Constrained Microprocessor Design. ICCD H. Peter Hofstee
2001	J	`jnl`	Derivation of a rotator circuit with homogeneous interconnect. Inf. Process. Lett. H. Peter Hofstee, Jun Sawada
2001	J	`jnl`	Timed circuit verification using TEL structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
2000	A*	`conf`	"Timing closure by design, " a high frequency microprocessor design methodology. DAC Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia
2000	J	`jnl`	Custom circuit design as a driver of microprocessor performance. IBM J. Res. Dev. David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel
1999	—	`conf`	Beyond 1 GHz. CICC H. Peter Hofstee, Kevin J. Nowka
1999	—	`conf`	Verification of Delayed-Reset Domino Circuits Using ATACS. ASYNC Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
1998	J	`jnl`	A 1.0-GHz single-issue 64-bit powerPC integer processor. IEEE J. Solid State Circuits Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric
1998	C	`conf`	A 690 ps read-access latency register file for a GHz integer microprocessor. ICCD Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, Naoaki Aoki
1998	C	`conf`	Design methodology for a 1.0 GHz microprocessor. ICCD Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo
1998	J	`jnl`	Designing for a gigahertz [guTS integer processor]. IEEE Micro H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi
1998	Misc	`conf`	High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. VTS David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz
1997	—	`conf`	Circuits and Microarchitecture for Gigahertz VLSI Designs. ARVLSI Kevin J. Nowka, H. Peter Hofstee
1995	—	`—`	Synchronizing processes. H. Peter Hofstee
1994	J	`jnl`	Distributing a Class of Sequential Programs. Sci. Comput. Program. H. Peter Hofstee
1992	B	`conf`	Distributing a Class of Sequential Programs. MPC H. Peter Hofstee
1991	—	`conf`	A Distributed Implementation of a Task Pool. Research Directions in High-Level Parallel Programming Languages H. Peter Hofstee, Johan J. Lukkien, Jan L. A. van de Snepscheut
1990	J	`jnl`	Distributed Sorting. Sci. Comput. Program. H. Peter Hofstee, Alain J. Martin, Jan L. A. van de Snepscheut