H.-S. Philip Wong

135 papers A* 14A 11B 1C 6Misc 2Journal 52Unranked 49

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler. CoRR Xinxin Wang, Lixian Yan, Shuhan Liu, Luke Upton, Zhuoqi Cai, Yiming Tan, Shengman Li, Koustav Jana, Peijing Li, Jesse Cirimelli-Low, Thierry Tambe, Matthew Guthaus, H.-S. Philip Wong
2026	J	`jnl`	Ultrafast Generative AI by Ultradense 3D Integration: A Case Study on LLM-based Edge Inference. ACM Trans. Design Autom. Electr. Syst. Kerem Akarvardar, Xiaoyu Sun, Brian Crafton, Xiaochen Peng, Haruki Mori, Abhiroop Bhattacharjee, Hidehiro Fujiwara, H.-S. Philip Wong
2025	J	`jnl`	GainSight: Application-Guided Profiling for Composing Heterogeneous On-Chip Memories in AI Hardware Accelerators. CoRR Peijing Li, Matthew Hung, Yiming Tan, Konstantin Hoßfeld, Jake Cheng Jiajun, Shuhan Liu, Lixian Yan, Xinxin Wang, H.-S. Philip Wong, Thierry Tambe
2025	J	`jnl`	OpenGCRAM: An Open-Source Gain Cell Compiler Enabling Design-Space Exploration for AI Workloads. CoRR Xinxin Wang, Lixian Yan, Shuhan Liu, Luke Upton, Zhuoqi Cai, Yiming Tan, Shengman Li, Koustav Jana, Peijing Li, Jesse Cirimelli-Low, Thierry Tambe, Matthew Guthaus, H.-S. Philip Wong
2025	J	`jnl`	The Future of Memory: Limits and Opportunities. CoRR Samuel Dayo, Shuhan Liu, Peijing Li, Philip Levis, Subhasish Mitra, Thierry Tambe, David Tennenhouse, H.-S. Philip Wong
2025	—	`conf`	Towards Memory Specialization: A Case for Long-Term and Short-Term RAM. DIMES@SOSP Peijing Li, Muhammad Shahir Abdurrahman, Rachel Cleaveland, Sergey Legtchenko, Philip Levis, Ioan A. Stefanovici, Thierry Tambe, David Tennenhouse, Caroline Trippel, H.-S. Philip Wong
2024	A*	`conf`	Bitwise Adaptive Early Termination in Hyperdimensional Computing Inference. DAC Wei-Chen Chen, H.-S. Philip Wong, Sara Achour
2024	A*	`conf`	Efficient Open Modification Spectral Library Searching in High-Dimensional Space with Multi-Level-Cell Memory. DAC Keming Fan, Wei-Chen Chen, Sumukh Pinge, H.-S. Philip Wong, Tajana Rosing
2024	J	`jnl`	Efficient Open Modification Spectral Library Searching in High-Dimensional Space with Multi-Level-Cell Memory. CoRR Keming Fan, Wei-Chen Chen, Sumukh Pinge, H.-S. Philip Wong, Tajana Rosing
2024	J	`jnl`	Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework. ACM Trans. Design Autom. Electr. Syst. Xiaoyu Sun, Xiaochen Peng, Sai Qian Zhang, Jorge Gomez, Win-San Khwa, Syed Shakib Sarwar, Ziyun Li, Weidong Cao, Zhao Wang, Chiao Liu, Meng-Fan Chang, Barbara De Salvo, Kerem Akarvardar, H.-S. Philip Wong
2024	—	`conf`	First Experimental Demonstration of Hybrid Gain Cell Memory with Si PMOS and ITO FET for High-speed On-chip Memory. VLSI Technology and Circuits Shuhan Liu, Shengjun Qin, Koustav Jana, Jian Chen, Kasidit Toprasertpong, H.-S. Philip Wong
2024	—	`conf`	High Performance Transistor of Aligned Carbon Nanotubes in a Nanosheet Structure. VLSI Technology and Circuits Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Shreyam Natani, San Lin Liew, Carlo Gilardi, Hsin-Yuan Chiu, Sheng-Kai Su, Andrew Bechdolt, Gilad Zeevi, Zichen Zhang, Matthias Passlack, Vincent D.-H. Hou, Harshil Kashyap, Chao-Hsin Chien, Prabhakar Bandaru, Andrew C. Kummel, H.-S. Philip Wong, Subhasish Mitra, Gregory Pitner, Iuliana P. Radu
2024	—	`conf`	On the Extreme Scaling of Transistors with Monolayer MOS2 Channel. VLSI Technology and Circuits Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Edward Chen, Chen-Feng Hsu, Walker Yun, Hsiang-Chi Hu, Bo-Heng Liu, T. Y. Lee, Chi-Chung Kei, Wen-Hao Chang, Jin Cai, W. Jeff, Chung-Cheng Wu, H.-S. Philip Wong, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu
2024	—	`conf`	Optimizing TiTe2/Ge4Sb6Te7 Superlattices Towards Low-Power, Fast-Speed, and High-Stability Phase Change Memory. DRC Xiangjin Wu, Asir Intisar Khan, H.-S. Philip Wong, Eric Pop
2024	—	`conf`	Positive Bias Stress Measurement Guideline and Band Analysis for Evaluating Instability of Oxide Semiconductor Transistors. VLSI Technology and Circuits Qi Jiang, Koustav Jana, Kasidit Toprasertpong, Shuhan Liu, H.-S. Philip Wong
2023	—	`conf`	Building high performance transistors on carbon nanotube channel. VLSI Technology and Circuits Gregory Pitner, Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Sheng-Kai Su, Gilad Zeevi, Qing Lin, Hsin-Yuan Chiu, Matthias Passlack, Zichen Zhang, D. Mahaveer Sathaiya, Aslan Wei, Carlo Gilardi, Edward Chen, San Lin Liew, Vincent D.-H. Hou, Chung-Wei Wu, Jeff Wu, Zhiwei Lin, Jeffrey Fagan, Ming Zheng, Han Wang, Subhasish Mitra, H.-S. Philip Wong, Iuliana P. Radu
2023	—	`conf`	Co-designed Capacitive Coupling-Immune Sensing Scheme for Indium-Tin-Oxide (ITO) 2T Gain Cell Operating at Positive Voltage Below 2 V. VLSI Technology and Circuits Kasidit Toprasertpong, Shuhan Liu, Jian Chen, Sumaiya Wahid, Koustav Jana, Wei-Chen Chen, Shengman Li, Eric Pop, H.-S. Philip Wong
2023	—	`conf`	First Observation of Ultra-high Polarization (~ 108 μC/cm²) in Nanometer Scaled High Performance Ferroelectric HZO Capacitors with Mo Electrodes. VLSI Technology and Circuits Fei Huang, B. Saini, L. Wan, H. Lu, X. He, S. Qin, Wilman Tsai, A. Gruverman, Andrew C. Meng, H.-S. Philip Wong, Paul C. McIntyre, Simon S. Wong
2023	—	`conf`	How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology. VLSI Technology and Circuits H.-L. Chiang, Richard A. Hadi, J.-F. Wang, Hung-Chi Han, J.-J. Wu, H.-H. Hsieh, J.-J. Horng, W.-S. Chou, B.-S. Lien, C.-H. Chang, Y.-C. Chen, Yeong-Her Wang, T.-C. Chen, J.-C. Liu, Y.-C. Liu, Meng-Hsueh Chiang, K.-H. Kao, B. Pulicherla, J. Cai, C.-S. Chang, K.-W. Su, K.-L. Cheng, T.-J. Yeh, Y.-C. Peng, Christian C. Enz, Mau-Chung Frank Chang, M.-F. Chang, H.-S. Philip Wong, Iuliana P. Radu
2023	J	`jnl`	Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities. Proc. IEEE Gert Cauwenberghs, Jason Cong, X. Sharon Hu, Siddharth Joshi, Subhasish Mitra, Wolfgang Porod, H.-S. Philip Wong
2023	J	`jnl`	Neural Network Compression for Noisy Storage Devices. ACM Trans. Embed. Comput. Syst. Berivan Isik, Kristy Choi, Xin Zheng, Tsachy Weissman, Stefano Ermon, H.-S. Philip Wong, Armin Alaghi
2023	—	`conf`	Scaled contact length with low contact resistance in monolayer 2D channel transistors. VLSI Technology and Circuits Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Dongxu Fan, Goutham Arutchelvan, Chen-Feng Hsu, Sheng-Kai Su, Ang-Sheng Chou, Edward Chen, Weisheng Li, Zhihao Yu, Hao Qiu, Ying-Mei Yang, Kuang-I Lin, Yun-Yang Shen, Wen-Hao Chang, San Lin Liew, Vincent D.-H. Hou, Jin Cai, Chung-Cheng Wu, Jeff Wu, H.-S. Philip Wong, Xinran Wang, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu
2023	J	`jnl`	Technology Prospects for Data-Intensive Computing. Proc. IEEE Kerem Akarvardar, H.-S. Philip Wong
2022	—	`conf`	4 Bits/cell Hybrid 1F1R for High Density Embedded Non-Volatile Memory and its Application for Compute in Memory. VLSI Technology and Circuits Wei-Chen Chen, Fei Huang, S. Qin, Z. Yu, Q. Lin, Paul C. McIntyre, Simon S. Wong, H.-S. Philip Wong
2022	—	`conf`	8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory. VLSI Technology and Circuits Shengjun Qin, Maryann C. Tung, Emma Belliveau, Shuhan Liu, Jimin Kwon, Wei-Chen Chen, Zizhen Jiang, S. Simon Wong, H.-S. Philip Wong
2022	J	`jnl`	A compute-in-memory chip based on resistive random-access memory. Nat. Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs
2022	—	`conf`	Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties. DRC Lauren Hoang, Alwin Daus, Sumaiya Wahid, Jimin Kwon, Jung-Soo Ko, Shengjun Qin, Mahnaz Islam, Krishna C. Saraswat, H.-S. Philip Wong, Eric Pop
2022	—	`conf`	First Demonstration of Ge2Sb2Te5-Based Superlattice Phase Change Memory with Low Reset Current Density (~3 MA/cm VLSI Technology and Circuits Asir Intisar Khan, Christopher Perez, Xiangjin Wu, Byoungjun Won, Kangsik Kim, Heungdong Kwon, Pranav Ramesh, Kathryn M. Neilson, Mehdi Asheghi, Krishna Saraswat, Zonghoon Lee, Il-Kwon Oh, H.-S. Philip Wong, Kenneth E. Goodson, Eric Pop
2022	—	`conf`	First Demonstration of Top-Gated ITO Transistors: Effect of Channel Passivation. DRC Sumaiya Wahid, Alwin Daus, Jimin Kwon, Shengjun Qin, Jung-Soo Ko, Krishna C. Saraswat, H.-S. Philip Wong, Eric Pop
2022	—	`conf`	First Fire-free, Low-voltage (~1.2 V), and Low Off-current (~3 nA) SiOxTey Selectors. VLSI Technology and Circuits S. Vaziri, I. M. Datye, Elia Ambrosi, Asir Intisar Khan, H. Kwon, C. H. Wu, C. F. Hsu, J. Guy, T. Y. Lee, H.-S. Philip Wong, X. Y. Bao
2022	J	`jnl`	High-density analog image storage in an analog-valued non-volatile memory array. Neuromorph. Comput. Eng. Xin Zheng, Ryan Zarcone, Akash Levy, Win-San Khwa, Priyanka Raina, Bruno A. Olshausen, H.-S. Philip Wong
2022	J	`jnl`	Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies. CoRR Richard A. Gottscho, Edlyn V. Levine, Tsu-Jae King Liu, Paul C. McIntyre, Subhasish Mitra, Boris Murmann, Jan M. Rabaey, Sayeef S. Salahuddin, Willy C. Shih, H.-S. Philip Wong
2022	—	`conf`	Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS. VLSI Technology and Circuits Sheng-Kai Su, Edward Chen, Terry Y. T. Hung, Meng-Zhan Li, Gregory Pitner, Chao-Ching Cheng, Han Wang, Jin Cai, H.-S. Philip Wong, Iuliana P. Radu
2022	—	`conf`	Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor. VLSI Technology and Circuits Ming-Yang Li, Ching-Hao Hsu, Shin-Wei Shen, Ang-Sheng Chou, Yuxuan Cosmi Lin, Chih-Piao Chuu, Ning Yang, Sui-An Chou, Lin-Yun Huang, Chao-Ching Cheng, Wei-Yen Woon, Szuya Liao, Chih-I Wu, Lain-Jong Li, Iuliana P. Radu, H.-S. Philip Wong, Han Wang
2021	J	`jnl`	Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. CoRR Chi-Shuen Lee, Brian Cline, Saurabh Sinha, Greg Yeric, H.-S. Philip Wong
2021	J	`jnl`	Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory. CoRR Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs
2021	J	`jnl`	Neural Network Compression for Noisy Storage Devices. CoRR Berivan Isik, Kristy Choi, Xin Zheng, Tsachy Weissman, Stefano Ermon, H.-S. Philip Wong, Armin Alaghi
2020	—	`conf`	33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. ISSCC Weier Wan, Rajkumar Kubendran, Sukru Burc Eryilmaz, Wenqiang Zhang, Yan Liao, Dabin Wu, Stephen R. Deiss, Bin Gao, Priyanka Raina, Siddharth Joshi, Huaqiang Wu, Gert Cauwenberghs, H.-S. Philip Wong
2020	—	`conf`	A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver. ICONS Rajkumar Kubendran, Weier Wan, Siddharth Joshi, H.-S. Philip Wong, Gert Cauwenberghs
2020	J	`jnl`	A Density Metric for Semiconductor Technology [Point of View]. Proc. IEEE H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin
2020	J	`jnl`	Nanotechnology-inspired Information Processing Systems of the Future. CoRR Randy Bryant, Mark D. Hill, Tom Kazior, Daniel Lee, Jie Liu, Klara Nahrstedt, Vijay Narayanan, Jan M. Rabaey, Hava T. Siegelmann, Naresh R. Shanbhag, Naveen Verma, H.-S. Philip Wong
2020	J	`jnl`	Scanning the Issue. Proc. IEEE H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin, Lei Deng, Xin-Guo Li, Song Han, Luping Shi, Yuan Xie, Elias Yaacoub, Mohamed-Slim Alouini, Ahmed Douik, Hayssam Dahrouj, Tareq Y. Al-Naffouri
2019	—	`conf`	A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques. ISSCC Tony F. Wu, Binh Q. Le, Robert M. Radway, Andrew Bartolo, William Hwang, Seungbin Jeong, Haitong Li, Pulkit Tandon, Elisa Vianello, Pascal Vivet, Etienne Nowak, Mary Wootters, H.-S. Philip Wong, Mohamed M. Sabry Aly, Edith Beigné, Subhasish Mitra
2019	—	`conf`	IC Technology - What Will the Next Node Offer Us? Hot Chips Symposium H.-S. Philip Wong
2019	J	`jnl`	Monolithic 3-D Integration. IEEE Micro Mindy D. Bishop, H.-S. Philip Wong, Subhasish Mitra, Max M. Shulaker
2019	A*	`conf`	On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators. DAC Haitong Li, Mudit Bhargava, Paul N. Whatmough, H.-S. Philip Wong
2019	J	`jnl`	The N3XT Approach to Energy-Efficient Abundant-Data Computing. Proc. IEEE Mohamed M. Sabry Aly, Tony F. Wu, Andrew Bartolo, Yash H. Malviya, William Hwang, Gage Hills, Igor L. Markov, Mary Wootters, Max M. Shulaker, H.-S. Philip Wong, Subhasish Mitra
2019	—	`conf`	Vertical Sidewall MoS2 Growth and Transistors. DRC Connor McClellan, Andrew C. Yu, Ching-Hua Wang, H.-S. Philip Wong, Eric Pop
2018	—	`conf`	Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study. ISSCC Tony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra
2018	C	`conf`	Coming Up N3XT, After 2D Scaling of Si CMOS. ISCAS William Hwang, Weier Wan, Subhasish Mitra, H.-S. Philip Wong
2018	—	`conf`	Energy-Efficient Phase Change Memory Programming by Nanosecond Pulses. DRC Eilam Yalon, Kye Okabe, Christopher M. Neumann, H.-S. Philip Wong, Eric Pop
2018	J	`jnl`	Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration. IEEE J. Solid State Circuits Tony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi, Gage Hills, Bryce Hodson, William Hwang, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra
2018	J	`jnl`	Hyperdimensional Computing Nanosystem. CoRR Abbas Rahimi, Tony F. Wu, Haitong Li, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra
2018	B	`conf`	Joint Source-Channel Coding with Neural Networks for Analog Data Compression and Storage. DCC Ryan Zarcone, Dylan M. Paiton, Alex Anderson, Jesse H. Engel, H.-S. Philip Wong, Bruno A. Olshausen
2018	—	`conf`	Low Power Nanoscale Switching of VO2using Carbon Nanotube Heaters. DRC Stephanie M. Bohaichuk, Miguel Munoz-Rojo, Gregory Pitner, Connor McClellan, Feifei Lian, Jason Li, Jaewoo Jeong, Mahesh Samant, Stuart Parkin, H.-S. Philip Wong, Eric Pop
2018	A*	`conf`	TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs. DAC Gage Hills, Daniel Bankman, Bert Moons, Lita Yang, Jake Hillard, Alex Kahng, Rebecca Park, Marian Verhelst, Boris Murmann, Max M. Shulaker, H.-S. Philip Wong, Subhasish Mitra
2018	—	`conf`	The End of the Road for 2D Scaling of Silicon CMOS and the Future of Device Technology. DRC H.-S. Philip Wong
2017	Misc	`conf`	3D nanosystems enable CODES+ISSS William Hwang, Mohamed M. Sabry Aly, Yash H. Malviya, Mingyu Gao, Tony F. Wu, Christos Kozyrakis, H.-S. Philip Wong, Subhasish Mitra
2017	A*	`conf`	A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. DAC Ameya Patil, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
2017	A*	`conf`	In Quest of the Next Information Processing Substrate: Extended Abstract: Invited. DAC Suman Datta, Alan C. Seabaugh, Michael T. Niemier, Arijit Raychowdhury, Darrell Schlom, Debdeep Jena, Huili Grace Xing, H.-S. Philip Wong, Eric Pop, Sayeef S. Salahuddin, Sumeet Kumar Gupta, Supratik Guha
2017	J	`jnl`	Opportunities for Analog Coding in Emerging Memory Systems. CoRR Jesse H. Engel, Sukru Burc Eryilmaz, Sangbum Kim, Matthew BrightSky, Chung Lam, Hsiang-Lan Lung, Bruno A. Olshausen, H.-S. Philip Wong
2017	J	`jnl`	Resistive RAM-Centric Computing: Design and Modeling Methodology. IEEE Trans. Circuits Syst. I Regul. Pap. Haitong Li, Tony F. Wu, Subhasish Mitra, H.-S. Philip Wong
2017	J	`jnl`	The End of Moore's Law: A New Beginning for Information Technology. Comput. Sci. Eng. Thomas N. Theis, H.-S. Philip Wong
2016	J	`jnl`	Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays. CoRR Haitong Li, Peng Huang, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong
2016	Misc	`conf`	Nano-engineered architectures for ultra-low power wireless body sensor nodes. CODES+ISSS Rubén Braojos, David Atienza, Mohamed M. Sabry Aly, Tony F. Wu, H.-S. Philip Wong, Subhasish Mitra, Giovanni Ansaloni
2016	—	`conf`	Neuromorphic architectures with electronic synapses. ISQED Sukru Burc Eryilmaz, Siddharth Joshi, Emre Neftci, Weier Wan, Gert Cauwenberghs, H.-S. Philip Wong
2016	J	`jnl`	TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tony F. Wu, Karthik Ganesan, Yunqing Alexander Hu, H.-S. Philip Wong, S. Simon Wong, Subhasish Mitra
2016	J	`jnl`	Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. Georges G. E. Gielen, Jelle Van Rethy, Jorge Marin, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra
2016	J	`jnl`	Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses. CoRR Sukru Burc Eryilmaz, Emre Neftci, Siddharth Joshi, Sangbum Kim, Matthew BrightSky, Hsiang-Lan Lung, Chung Lam, Gert Cauwenberghs, H.-S. Philip Wong
2016	—	`conf`	Transforming nanodevices to next generation nanosystems. SAMOS Max Marcel Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra
2015	—	`conf`	Contact pitch and location prediction for Directed Self-Assembly template verification. ASP-DAC Zigang Xiao, Yuelin Du, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang
2015	J	`jnl`	Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures. CoRR Sukru Burc Eryilmaz, Duygu Kuzum, Shimeng Yu, H.-S. Philip Wong
2015	J	`jnl`	Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x. Computer Mohamed M. Sabry, Mingyu Gao, Gage Hills, Chi-Shuen Lee, Greg Pitner, Max M. Shulaker, Tony F. Wu, Mehdi Asheghi, Jeffrey Bokor, Franz Franchetti, Kenneth E. Goodson, Christos Kozyrakis, Igor L. Markov, Kunle Olukotun, Larry T. Pileggi, Eric Pop, Jan M. Rabaey, Christopher Ré, H.-S. Philip Wong, Subhasish Mitra
2015	A*	`conf`	Layout optimization and template pattern verification for directed self-assembly (DSA). DAC Zigang Xiao, Daifeng Guo, Martin D. F. Wong, He Yi, Maryann C. Tung, H.-S. Philip Wong
2015	—	`conf`	Modeling and design optimization of ReRAM. ASP-DAC Jinfeng Kang, Haitong Li, Peng Huang, Zhe Chen, Bin Gao, Xiaoyan Liu, Zizhen Jiang, H.-S. Philip Wong
2015	A	`conf`	Monolithic 3D integration: a path from concept to reality. DATE Max M. Shulaker, Tony F. Wu, Mohamed M. Sabry, Hai Wei, H.-S. Philip Wong, Subhasish Mitra
2015	—	`conf`	Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning. ISPD H.-S. Philip Wong, He Yi, Maryann C. Tung, Kye Okabe
2015	—	`conf`	RRAM based synaptic devices for neuromorphic visual systems. DSP Jinfeng Kang, Bin Gao, Peng Huang, Lifeng Liu, Xiaoyan Liu, H. Y. Yu, Shimeng Yu, H.-S. Philip Wong
2015	J	`jnl`	Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra
2015	J	`jnl`	Rapid Co-optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations. CoRR Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra
2015	J	`jnl`	TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits. CoRR Tony F. Wu, Karthik Ganesan, Yunqing Alexander Hu, H.-S. Philip Wong, S. Simon Wong, Subhasish Mitra
2015	C	`conf`	Time-based sensor interface circuits in carbon nanotube technology. ISCAS Georges G. E. Gielen, Jelle Van Rethy, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra
2015	A	`conf`	Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model. DATE Haitong Li, Zizhen Jiang, Peng Huang, Y. Wu, Hong-Yu Chen, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong
2014	J	`jnl`	Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array. CoRR Sukru Burc Eryilmaz, Duygu Kuzum, Rakesh Gnana David Jeyasingh, Sangbum Kim, Matthew BrightSky, Chung Lam, H.-S. Philip Wong
2014	C	`conf`	Design considerations of synaptic device for neuromorphic computing. ISCAS Shimeng Yu, Duygu Kuzum, H.-S. Philip Wong
2014	C	`conf`	Design guidelines for 3D RRAM cross-point architecture. ISCAS Shimeng Yu, Yexin Deng, Bin Gao, Peng Huang, Bing Chen, Xiaoyan Liu, Jinfeng Kang, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong
2014	A*	`conf`	Directed Self-Assembly (DSA) Template Pattern Verification. DAC Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang
2014	J	`jnl`	Experimental Demonstration of Array-level Learning with Phase Change Synaptic Devices. CoRR Sukru Burc Eryilmaz, Duygu Kuzum, Rakesh Gnana David Jeyasingh, Sangbum Kim, Matthew BrightSky, Chung Lam, H.-S. Philip Wong
2014	—	`conf`	Robust design and experimental demonstrations of carbon nanotube digital circuits. CICC Gage Hills, Max M. Shulaker, Hai Wei, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra
2014	C	`conf`	Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture. ISCAS Jinfeng Kang, Bin Gao, Bing Chen, Peng Huang, Feifei Zhang, Xiaoyan Liu, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong, Shimeng Yu
2014	J	`jnl`	Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs. IEEE J. Solid State Circuits Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hai Wei, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra
2014	J	`jnl`	System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits. ACM J. Emerg. Technol. Comput. Syst. Shashikanth Bobba, Jie Zhang, Pierre-Emmanuel Gaillardon, H.-S. Philip Wong, Subhasish Mitra, Giovanni De Micheli
2014	A	`conf`	Video analytics using beyond CMOS devices. DATE Vijaykrishnan Narayanan, Suman Datta, Gert Cauwenberghs, Donald M. Chiarulli, Steven P. Levitan, H.-S. Philip Wong
2013	A	`conf`	Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library. ICCAD Yuelin Du, Daifeng Guo, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang, Qiang Ma
2013	A	`conf`	Carbon nanotube circuits: opportunities and challenges. DATE Hai Wei, Max M. Shulaker, Gage Hills, Hong-Yu Chen, Chi-Shuen Lee, Luckshitha Liyanage, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra
2013	J	`jnl`	Combinational Logic Design Using Six-Terminal NEM Relays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daesung Lee, W. Scott Lee, Chen Chen, Farzan Fallah, J. Provine, Soogine Chong, John Watkins, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra
2013	J	`jnl`	Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array. ACM J. Emerg. Technol. Comput. Syst. Jiale Liang, Chih-Wei Stanley Yeh, S. Simon Wong, H.-S. Philip Wong
2013	—	`conf`	Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs. ISSCC Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra
2013	J	`jnl`	Impact of III-V and Ge Devices on Circuit Performance. IEEE Trans. Very Large Scale Integr. Syst. Jeongha Park, Saeroonter Oh, Soyoung Kim, H.-S. Philip Wong, S. Simon Wong
2013	A*	`conf`	Rapid exploration of processing and design guidelines to overcome carbon nanotube variations. DAC Gage Hills, Jie Zhang, Charles Mackin, Max M. Shulaker, Hai Wei, H.-S. Philip Wong, Subhasish Mitra
2013	A*	`conf`	Sacha: the Stanford carbon nanotube controlled handshaking robot. DAC Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra
2012	J	`jnl`	Carbon Nanotube Robust Digital VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra
2012	—	`conf`	Interconnect scaling into the sub-10nm regime. SLIP Xiangyu Chen, Jiale Liang, H.-S. Philip Wong
2012	J	`jnl`	Metal-Oxide RRAM. Proc. IEEE H.-S. Philip Wong, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, Ming-Jinn Tsai
2012	—	`conf`	Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing. ASP-DAC Chen Chen, W. Scott Lee, J. Provine, Soogine Chong, Roozbeh Parsa, Daesung Lee, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra
2012	A	`conf`	Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique. DATE Chen Chen, W. Scott Lee, Roozbeh Parsa, Soogine Chong, J. Provine, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra
2012	—	`conf`	Phase Change Memory: Scaling and applications. CICC Rakesh Gnana David Jeyasingh, Jiale Liang, Marissa Caldwell, Duygu Kuzum, H.-S. Philip Wong
2011	A	`conf`	Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated. ICCAD Hai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra
2011	J	`jnl`	Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jie Zhang, Nishant Patil, Arash Hazeghi, H.-S. Philip Wong, Subhasish Mitra
2011	—	`conf`	Circuit-aware device reliability criteria methodology. ESSCIRC Jason T. Ryan, Lan Wei, Jason P. Campbell, Ricki G. Southwick, Kin P. Cheung, Anthony S. Oates, H.-S. Philip Wong, John Suehle
2010	A	`conf`	Carbon nanotube circuits: Living with imperfections and variations. DATE Jie Zhang, Nishant Patil, Albert Lin, H.-S. Philip Wong, Subhasish Mitra
2010	A*	`conf`	Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. DAC Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra
2010	A*	`conf`	Detachable nano-carbon chip with ultra low power. DAC Shinobu Fujita, Shinichi Yasuda, Daesung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong
2010	A	`conf`	Efficient FPGAs using nanoelectromechanical relays. FPGA Chen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra
2010	—	`conf`	Intel LVS logic as a combinational logic paradigm in CNT technology. NANOARCH Bao Liu, Zhen Cao, Jun Tao, Xuan Zeng, Pushan Tang, H.-S. Philip Wong
2010	—	`conf`	Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design. ISQED Saeroonter Oh, Jeongha Park, S. Simon Wong, H.-S. Philip Wong
2010	J	`jnl`	Phase Change Memory. Proc. IEEE H.-S. Philip Wong, Simone Raoux, Sangbum Kim, Jiale Liang, John P. Reifenberg, Bipin Rajendran, Mehdi Asheghi, Kenneth E. Goodson
2009	A*	`conf`	Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. DAC Nishant Patil, Albert Lin, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra
2009	C	`conf`	Fabrication and Characterization of Emerging Nanoscale Memory. ISCAS Sangbum Kim, Yuan Zhang, Byoungil Lee, Marissa Caldwell, H.-S. Philip Wong
2009	A	`conf`	Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage. ICCAD Soogine Chong, Kerem Akarvardar, Roozbeh Parsa, Jun-Bo Yoon, Roger T. Howe, Subhasish Mitra, H.-S. Philip Wong
2008	—	`conf`	A 3MPixel Multi-Aperture Image Sensor with 0.7μm Pixels in 0.11μm CMOS. ISSCC Keith Fife, Abbas El Gamal, H.-S. Philip Wong
2008	J	`jnl`	A Multi-Aperture Image Sensor With 0.7 µm Pixels in 0.11 µm CMOS Technology. IEEE J. Solid State Circuits Keith Fife, Abbas El Gamal, H.-S. Philip Wong
2008	J	`jnl`	Carbon nanotube transistor compact model for circuit design and performance optimization. ACM J. Emerg. Technol. Comput. Syst. Jie Deng, Albert Lin, Gordon C. Wan, H.-S. Philip Wong
2008	J	`jnl`	Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra
2007	A*	`conf`	Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits. DAC Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra
2007	—	`conf`	Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections. ISSCC Jie Deng, Nishant Patil, Koungmin Ryu, Alexander Badmaev, Chongwu Zhou, Subhasish Mitra, H.-S. Philip Wong
2007	—	`conf`	Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. ISQED Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong
2006	—	`conf`	A 3D Multi-Aperture Image Sensor Architecture. CICC Keith Fife, Abbas El Gamal, H.-S. Philip Wong
2006	A	`conf`	Carbon nanotube transistor circuits: models and tools for design and performance optimization. ICCAD H.-S. Philip Wong, Jie Deng, Arash Hazeghi, Tejas Krishnamohan, Gordon C. Wan
2006	—	`conf`	Device and Technology Challenges for Nanoscale CMOS. ISQED H.-S. Philip Wong
2005	—	`conf`	Nanoelectronics: nanotubes, nanowires, molecules, and novel concepts. ESSCIRC H.-S. Philip Wong
2002	J	`jnl`	Beyond the conventional transistor. IBM J. Res. Dev. H.-S. Philip Wong
2002	—	`conf`	High Performance Double-Gate Device Technology Challenges and Opportunities (invited). ISQED Meikei Leong, H.-S. Philip Wong, Edward J. Nowak, Jakub Kedzierski, Erin C. Jones
1998	J	`jnl`	Digital Imaging. IEEE Micro H.-S. Philip Wong, Albert J. P. Theuwissen
1995	J	`jnl`	CMOS scaling into the 21st century: 0.1 µm and beyond. IBM J. Res. Dev. Yuan Taur, Yuh-Jier Mii, David J. Frank, H.-S. Philip Wong, Douglas A. Buchanan, Shalom J. Wind, Stephen A. Rishton, Watson A. Sai-Halasz, Edward J. Nowak