Görschwin Fey

212 papers A* 3A 13B 11C 56Misc 5Journal 37Unranked 82

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Ageing Monitoring for Commercial Microcontrollers Based on Timing Windows. CoRR Leandro Lanzieri, Jirí Král, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt
2026	J	`jnl`	Flowcean - Model Learning for Cyber-Physical Systems. CoRR Maximilian Schmidt, Swantje Plambeck, Markus Knitt, Hendrik Rose, Görschwin Fey, Jan Christian Wieck, Stephan Balduin
2026	J	`jnl`	Identification of hybrid systems with dynamics-based modeling through symbolic regression. J. Syst. Softw. Swantje Plambeck, Maximilian Schmidt, Audine Subias, Louise Travé-Massuyès, Görschwin Fey
2025	J	`jnl`	A Review of Techniques for Ageing Detection and Monitoring on Embedded Systems. ACM Comput. Surv. Leandro Lanzieri, Gianluca Martino, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt, Matthias Wählisch
2025	J	`jnl`	Data-Driven Probabilistic Evaluation of Logic Properties with PAC-Confidence on Mealy Machines. CoRR Swantje Plambeck, Ali Salamati, Eyke Hüllermeier, Görschwin Fey
2025	Misc	`conf`	DuRTL - Information Flow Analysis Tool for Register Transfer Level Hardware Designs. VLSID Lutz Schammer, Gianluca Martino, Görschwin Fey
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	C	`conf`	Leveraging the Benefits of Information Flow Tracking for Detecting Hardware Design Flaws. FDL Srinidhi Rathnakar Ganiga, Bernhard J. Berger, Görschwin Fey
2025	C	`conf`	One-Shot Learning in Hybrid System Identification: A New Modular Paradigm. DX Swantje Plambeck, Maximilian Schmidt, Louise Travé-Massuyès, Görschwin Fey
2025	A	`conf`	Specification Mining Facing Generative AI. DATE Görschwin Fey, Harry Foster, Tara Ghasempuri, Badri Gopalan, Jörg Müller, Manish Pandey
2024	C	`conf`	Data-Driven Fault Localization in Cyber-Physical Systems Using Dependency Graphs and Anomaly Detection. EJC Arne Grünhagen, Annika Eichler, Marina Tropmann-Frick, Görschwin Fey
2024	J	`jnl`	Detailed insight into approximate circuits with error-responsive information flow tracking. it Inf. Technol. Lutz Schammer, Gianluca Martino, Amir Najafi, Alberto García Ortiz, Görschwin Fey
2024	B	`conf`	Dynamics-Based Identification of Hybrid Systems using Symbolic Regression. SEAA Swantje Plambeck, Maximilian Schmidt, Görschwin Fey, Audine Subias, Louise Travé-Massuyès
2024	—	`conf`	Evaluating the Performance of Large Language Models for Design Validation. SOCC Abdur Rahman, Görschwin Fey
2024	—	`conf`	FaMoS- Fast Model Learning for Hybrid Cyber-Physical Systems using Decision Trees. HSCC Swantje Plambeck, Aaron Bracht, Nemanja Hranisavljevic, Görschwin Fey
2024	—	`conf`	Hardware-accelerated Compression Core on RISC-V for Online-BCG Data Reduction. NorCAS Kazi Mohammad Abidur Rahman, Abdelrahman Noshy Abdelalim Ahmed, Görschwin Fey, Ulf Kulau
2024	J	`jnl`	Solving Boolean Problems and Beyond. it Inf. Technol. Rolf Drechsler, Görschwin Fey
2024	C	`conf`	Studying the Degradation of Propagation Delay on FPGAs at the European XFEL. DSD Leandro Lanzieri, Lukasz Butkowski, Jirí Král, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt
2024	J	`jnl`	Studying the Degradation of Propagation Delay on FPGAs at the European XFEL. CoRR Leandro Lanzieri, Lukasz Butkowski, Jirí Král, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt
2024	J	`jnl`	Switching Frequency as FPGA Monitor: Studying Degradation and Ageing Prognosis at Large Scale. CoRR Leandro Lanzieri, Lukasz Butkowski, Jirí Král, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt
2024	C	`conf`	Usability of Symbolic Regression for Hybrid System Identification - System Classes and Parameters (Short Paper). DX Swantje Plambeck, Maximilian Schmidt, Audine Subias, Louise Travé-Massuyès, Görschwin Fey
2024	—	`conf`	Usage Driven Relevance Analysis for IP Cores. SOCC Lutz Schammer, Gianluca Martino, Görschwin Fey
2023	J	`jnl`	A Review of Techniques for Ageing Detection and Monitoring on Embedded Systems. CoRR Leandro Lanzieri, Gianluca Martino, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt, Matthias Wählisch
2023	C	`conf`	Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine Learning. DSD Leandro Lanzieri, Peter Kietzmann, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt
2023	J	`jnl`	Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine Learning. CoRR Leandro Lanzieri, Peter Kietzmann, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt
2023	A	`conf`	DEL: Dynamic Symbolic Execution-based Lifter for Enhanced Low-Level Intermediate Representation. DATE Hany Abdelmaksoud, Zain Alabedin Haj Hammadeh, Görschwin Fey, Daniel Lüdtke
2023	C	`conf`	Data-Based Condition Monitoring and Disturbance Classification in Actively Controlled Laser Oscillators. EJC Arne Grünhagen, Annika Eichler, Marina Tropmann-Frick, Görschwin Fey
2023	C	`conf`	Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models. DDECS Swantje Plambeck, Görschwin Fey
2023	—	`conf`	Enhancing Data Acquisition and Fault Analysis for Large-Scale Facilities: A Case Study on the Laser-Based Synchronization System at the European X-Ray Free-Electron Laser. LWDA Arne Grünhagen, Maximilian Schütte, Annika Eichler, Marina Tropmann-Frick, Görschwin Fey
2023	B	`conf`	FINaL: Driving High-Level Fault Injection Campaigns with Natural Language. ETS Khaled Galal Abdelwahab Abdelaziz, Ralph Görgen, Görschwin Fey
2023	—	`conf`	GLRP: Guided by Layer-wise Relevance Propagation - Selecting Crucial Neurons in Artificial Neural Networks. MOCAST Fin Hendrik Bahnsen, Bernhard J. Berger, Görschwin Fey
2023	—	`conf`	Informatik für Ingenieure an der Technischen Universität Hamburg. GI-Jahrestagung Bernhard J. Berger, Görschwin Fey
2023	C	`conf`	Latency-Optimized Hardware Acceleration of Multilayer Perceptron Inference. DSD Ahmad Al-Zoubi, Benedikt Schaible, Gianluca Martino, Görschwin Fey
2023	Misc	`conf`	Predictive Maintenance for the Optical Synchronization System of the European XFEL: A Systematic Literature Survey. BTW Arne Grünhagen, Marina Tropmann-Frick, Annika Eichler, Görschwin Fey
2023	C	`conf`	Towards the Automatic Generation of Models for Prediction, Monitoring, and Testing of Cyber-Physical Systems. ETFA Markus Knitt, Swantje Plambeck, Jan Christian Wieck, Julian Kohlisch, Stephan Balduin, Eric M. S. P. Veith, Jakob Schyga, Johannes Hinckeldeyn, Görschwin Fey, Jochen Kreutzfeldt
2022	—	`conf`	CNN Implementation and Analysis on Xilinx Versal ACAP at European XFEL. SOCC Ahmad Al-Zoubi, Gianluca Martino, Fin Hendrik Bahnsen, Jun Zhu, Holger Schlarb, Görschwin Fey
2022	C	`conf`	Decision Tree Models of Continuous Systems. ETFA Swantje Plambeck, Görschwin Fey
2022	C	`conf`	Decision Trees for Analyzing Influences on the Accuracy of Indoor Localization Systems. IPIN Jakob Schyga, Swantje Plambeck, Johannes Hinckeldeyn, Görschwin Fey, Jochen Kreutzfeldt
2022	J	`jnl`	Decision Trees for Analyzing Influences on the Accuracy of Indoor Localization Systems. CoRR Jakob Schyga, Swantje Plambeck, Johannes Hinckeldeyn, Görschwin Fey, Jochen Kreutzfeldt
2022	—	`conf`	Design Understanding: Identifying Instruction Pipelines in Hardware Designs. MOCAST Lutz Schammer, Jan Runge, Paula Klimach, Görschwin Fey
2022	—	`conf`	On the Viability of Decision Trees for Learning Models of Systems. ASP-DAC Swantje Plambeck, Lutz Schammer, Görschwin Fey
2022	—	`conf`	Regression Trees for System Models and Prediction. OVERLAY@AI*IA Swantje Plambeck, Görschwin Fey
2022	—	`conf`	Runtime Monitoring of c-LTL Specifications on FPGAs Using HLS. SMACD Gianluca Martino, Görschwin Fey
2022	—	`conf`	Self-Explanation in Systems of Systems. RE Workshops Görschwin Fey, Martin Fränzle, Rolf Drechsler
2021	J	`jnl`	Automata Learning for Automated Test Generation of Real Time Localization Systems. CoRR Swantje Plambeck, Jakob Schyga, Johannes Hinckeldeyn, Jochen Kreutzfeldt, Görschwin Fey
2021	C	`conf`	Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems. DSD Gianluca Martino, Arne Grünhagen, Julien Branlard, Annika Eichler, Görschwin Fey, Holger Schlarb
2021	B	`conf`	Designing Recurrent Neural Networks for Monitoring Embedded Devices. ETS Fin Hendrik Bahnsen, Jan Kaiser, Görschwin Fey
2021	—	`conf`	Effect Analysis of Low-Level Hardware Faults on Neural Networks using Emulated Inference. MOCAST Fin Hendrik Bahnsen, Vanessa Klebe, Görschwin Fey
2021	—	`conf`	Fault Analysis of the Beam Acceleration Control System at the European XFEL using Data Mining. ATS Arne Grünhagen, Julien Branlard, Annika Eichler, Gianluca Martino, Görschwin Fey, Marina Tropmann-Frick
2021	B	`conf`	Learning Models of Cyber-Physical Systems using Automata Learning. COMPSAC Lutz Schammer, Swantje Plambeck, Fin Hendrik Bahnsen, Görschwin Fey
2021	C	`conf`	Metrics for the Evaluation of Approximate Sequential Streaming Circuits. DSD Swantje Plambeck, Gianluca Martino, Görschwin Fey
2021	—	`conf`	YAPS - Your Open Examination System for Activating and emPowering Students. ICCSE Fin Hendrik Bahnsen, Görschwin Fey
2021	J	`jnl`	YAPS - Your Open Examination System for Activating and emPowering Students. CoRR Fin Hendrik Bahnsen, Görschwin Fey
2020	C	`conf`	Revisiting Explicit Enumeration for Exact Synthesis. DSD Gianluca Martino, Heinz Riener, Görschwin Fey
2019	—	`conf`	Approximation of Neural Networks for Verification. MBMV Fin Hendrik Bahnsen, Görschwin Fey
2019	C	`conf`	Engineering of an Effective Automatic Dynamic Assertion Mining Platform. VLSI-SoC Tara Ghasempouri, Jan Malburg, Alessandro Danese, Graziano Pravadelli, Görschwin Fey, Jaan Raik
2019	C	`conf`	Local Monitoring of Embedded Applications and Devices using Artificial Neural Networks. DSD Fin Hendrik Bahnsen, Görschwin Fey
2019	—	`conf`	Self-Explaining Digital Systems - Some Technical Steps. MBMV Görschwin Fey, Rolf Drechsler
2019	B	`conf`	Symbolic Circuit Analysis under an Arc Based Timing Model. ETS Görschwin Fey, Alberto García Ortiz
2019	C	`conf`	Syntax-Guided Enumeration of Temporal Properties. FDL Gianluca Martino, Görschwin Fey
2019	J	`jnl`	Synthesizing adaptive test strategies from temporal logic specifications. Formal Methods Syst. Des. Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Könighofer, Ingo Pill, Heinz Riener, Franz Röck
2018	C	`conf`	Augmenting All Solution SAT Solving for Circuits with Structural Information. DDECS Abraham Temesgen Tibebu, Görschwin Fey
2018	C	`conf`	Design Understanding: From Logic to Specification VLSI-SoC Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener
2018	—	`conf`	Mining Latency Guarantees for RTL Designs. ISMVL Jan Malburg, Heinz Riener, Görschwin Fey
2018	C	`conf`	Software-Level TMR Approach for On-Board Data Processing in Space Applications. DDECS Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Görschwin Fey
2018	J	`jnl`	Synthesizing Adaptive Test Strategies from Temporal Logic Specifications. CoRR Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Könighofer, Ingo Pill, Heinz Riener, Franz Röck
2018	—	`conf`	Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation. IVSW Rolf Drechsler, Christoph Lüth, Görschwin Fey, Tim Güneysu
2017	J	`jnl`	A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. J. Electron. Test. Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey
2017	—	`conf`	CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification. ASP-DAC Heinz Riener, Rüdiger Ehlers, Görschwin Fey
2017	—	`conf`	Counterexample-Guided EF Synthesis of Boolean Functions. MBMV Heinz Riener, Rüdiger Ehlers, Görschwin Fey
2017	J	`jnl`	Empirical results on parity-based soft error detection with software-based retry. Microprocess. Microsystems Gökçe Aydos, Görschwin Fey
2017	C	`conf`	Mapping abstract and concrete hardware models for design understanding. DDECS Tino Flenker, Görschwin Fey
2017	—	`conf`	Property mining using dynamic dependency graphs. ASP-DAC Jan Malburg, Tino Flenker, Görschwin Fey
2017	C	`conf`	Temporal redundancy latch-based architecture for soft error mitigation. IOLTS Robert Schmidt, Alberto García Ortiz, Görschwin Fey
2017	—	`conf`	Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. ISVLSI Tino Flenker, Jan Malburg, Görschwin Fey, Serhiy Avramenko, Massimo Violante, Matteo Sonza Reorda
2017	J	`jnl`	metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
2016	—	`conf`	A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. ISVLSI Niels Thole, Görschwin Fey, Alberto García Ortiz
2016	B	`conf`	A hybrid algorithm to conservatively check the robustness of circuits. ETS Niels Thole, Lorena Anghel, Görschwin Fey
2016	—	`conf`	Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables. LATS Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey
2016	—	`conf`	Counterexample-guided diagnosis. IVSW Heinz Riener, Görschwin Fey
2016	J	`jnl`	Debugging hardware designs using dynamic dependency graphs. Microprocess. Microsystems Jan Malburg, Alexander Finder, Görschwin Fey
2016	C	`conf`	Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
2016	C	`conf`	Equivalence checking on ESL utilizing a priori knowledge. FDL Niels Thole, Heinz Riener, Görschwin Fey
2016	A	`conf`	Exact diagnosis using boolean satisfiability. ICCAD Heinz Riener, Görschwin Fey
2016	C	`conf`	Exploiting error detection latency for parity-based soft error detection. DDECS Gökçe Aydos, Görschwin Fey
2016	A	`conf`	Multilevel design understanding: from specification to logic (invited paper). ICCAD Sandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken
2016	C	`conf`	On the robustness of DCT-based compression algorithms for space applications. IOLTS Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey, Jan-Gerd Mess, Robert Schmidt
2016	—	`conf`	SMT-Based CPS Parameter Synthesis. ARCH@CPSWeek Heinz Riener, Robert Könighofer, Görschwin Fey, Roderick Bloem
2016	—	`conf`	Umgebung für automatisierte Tests von Dateisystemen auf NAND-Flash-Speichern. Echtzeit Pascal Pieper, Fabian Greif, Görschwin Fey
2016	C	`conf`	WCET overapproximation for software in the context of a Cyber-Physical System. VLSI-SoC Niklas Krafczyk, Heinz Riener, Görschwin Fey
2015	—	`conf`	Conservatively Analyzing Transient Faults. ISVLSI Niels Thole, Görschwin Fey, Alberto García Ortiz
2015	—	`conf`	Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation. ATS Tino Flenker, André Sülflow, Görschwin Fey
2015	—	`conf`	Empirical results on parity-based soft error detection with software-based retry. NORCAS Gökçe Aydos, Görschwin Fey
2015	C	`conf`	Equivalence Checking on System Level Using a Priori Knowledge. DDECS Niels Thole, Heinz Riener, Görschwin Fey
2015	—	`conf`	Execution Tracing of C Code for Formal Analysis (Extended Abstract). MBMV Heinz Riener, Michael Kirkedal Thomsen, Görschwin Fey
2015	—	`conf`	Formal Verification of Robustness. SyDe Summer School Niels Thole, Görschwin Fey
2015	—	`conf`	In-circuit Error Detection with Software-based Error Correction - An Alternative to TMR. SyDe Summer School Gökçe Aydos, Görschwin Fey
2015	—	`conf`	Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture. GI-Jahrestagung Gökçe Aydos, Görschwin Fey
2015	—	`conf`	Path-Based Program Repair. FESCA Heinz Riener, Rüdiger Ehlers, Görschwin Fey
2015	J	`jnl`	Transaction-based online debug for NoC-based multiprocessor SoCs. Microprocess. Microsystems Mehdi Dehbashi, Görschwin Fey
2014	—	`conf`	A Logic for Cardinality Constraints (Extended Abstract). MBMV Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey
2014	J	`jnl`	A Simulation-Based Approach for Automated Feature Localization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jan Malburg, Alexander Finder, Görschwin Fey
2014	C	`conf`	Automatically connecting hardware blocks via light-weight matching techniques. DDECS Jan Malburg, Niklas Krafczyk, Görschwin Fey
2014	Misc	`conf`	Debug Automation for Synchronization Bugs at RTL. VLSID Mehdi Dehbashi, Görschwin Fey
2014	—	`conf`	Equivalence Checking on System Level using Stepwise Induction. MBMV Niels Thole, Görschwin Fey
2014	J	`jnl`	Latency Analysis for Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alexander Finder, André Sülflow, Görschwin Fey
2014	C	`conf`	MetaSMT: a unified interface to SMT-LIB2. FDL Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
2014	—	`conf`	Mutation Based Feature Localization. MTV Jan Malburg, Emmanuelle Encrenaz-Tiphène, Görschwin Fey
2014	—	`conf`	SAT-based speedpath debugging using X traces. IDT Mehdi Dehbashi, Görschwin Fey
2014	B	`conf`	Sat-based speedpath debugging using waveforms. ETS Mehdi Dehbashi, Görschwin Fey
2014	C	`conf`	Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs. PDP Mehdi Dehbashi, Görschwin Fey
2013	C	`ed.`	16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013 DDECS Lukás Sekanina, Görschwin Fey, Jaan Raik, Snorre Aunet, Richard Ruzicka
2013	J	`jnl`	Automated design debugging in a testbench-based verification environment. Microprocess. Microsystems Mehdi Dehbashi, André Sülflow, Görschwin Fey
2013	J	`jnl`	Debug Automation for Logic Circuits Under Timing Variations. IEEE Des. Test Mehdi Dehbashi, Görschwin Fey
2013	C	`conf`	Debugging HDL designs based on functional equivalences with high-level specifications. DDECS Alexander Finder, Jan-Philipp Witte, Görschwin Fey
2013	C	`conf`	Efficient automated speedpath debugging. DDECS Mehdi Dehbashi, Görschwin Fey
2013	J	`jnl`	Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. Daniel Große, Görschwin Fey, Rolf Drechsler
2013	A	`conf`	Improving fault tolerance utilizing hardware-software-co-synthesis. DATE Heinz Riener, Stefan Frehse, Görschwin Fey
2013	A	`conf`	Reliability analysis reloaded: how will we survive? DATE Robert C. Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda
2013	A	`conf`	Tuning dynamic data flow analysis to support design understanding. DATE Jan Malburg, Alexander Finder, Görschwin Fey
2013	—	`conf`	Yet a Better Error Explanation Algorithm (Extended Abstract). MBMV Heinz Riener, Görschwin Fey
2012	—	`conf`	Automated Feature Localization for Hardware Designs using Coverage Metrics. MBMV Jan Malburg, Alexander Finder, Görschwin Fey
2012	—	`conf`	Automated Post-Silicon Debugging of Failing Speedpaths. Asian Test Symposium Mehdi Dehbashi, Görschwin Fey
2012	C	`conf`	Automated debugging from pre-silicon to post-silicon. DDECS Mehdi Dehbashi, Görschwin Fey
2012	A*	`conf`	Automated feature localization for hardware designs using coverage metrics. DAC Jan Malburg, Alexander Finder, Görschwin Fey
2012	B	`conf`	Complete and effective robustness checking by means of interpolation. FMCAD Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler
2012	—	`conf`	FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation. SPIN Heinz Riener, Görschwin Fey
2012	—	`conf`	FoREnSiC- An Automatic Debugging Environment for C Programs. Haifa Verification Conference Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
2012	B	`conf`	Functional analysis of circuits under timing variations. ETS Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
2012	C	`conf`	Model-based diagnosis versus error explanation. MEMOCODE Heinz Riener, Görschwin Fey
2012	C	`conf`	On Modeling and Evaluation of Logic Circuits under Timing Variations. DSD Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
2012	J	`jnl`	Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports Görschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik Roy, Matteo Sonza Reorda
2011	—	`conf`	Assessing System Vulnerability Using Formal Verification Techniques. MEMICS Görschwin Fey
2011	C	`conf`	Automated Design Debugging in a Testbench-Based Verification Environment. DSD Mehdi Dehbashi, André Sülflow, Görschwin Fey
2011	C	`conf`	Automatic property generation for the formal verification of bus bridges. DDECS Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
2011	J	`jnl`	Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
2011	B	`conf`	Latency Analysis for Sequential Circuits. ETS Alexander Finder, André Sülflow, Görschwin Fey
2011	A*	`conf`	Orchestrated multi-level information flow analysis to understand SoCs. DAC Görschwin Fey
2011	—	`conf`	Test Case Generation from Mutants Using Model Checking Techniques. ICST Workshops Heinz Riener, Roderick Bloem, Görschwin Fey
2011	—	`conf`	Towards Automatic Property Generation for the Formal Verification of Bus Bridges. MBMV Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
2011	—	`conf`	metaSMT: Focus on Your Application not on Solver Integration. DIFTS@FMCAD Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler
2010	C	`conf`	A better-than-worst-case robustness measure. DDECS Stefan Frehse, Görschwin Fey, Rolf Drechsler
2010	J	`jnl`	Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). it Inf. Technol. Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
2010	C	`conf`	Evaluating Debugging Algorithms from a Qualitative Perspective. FDL Alexander Finder, Görschwin Fey
2010	C	`conf`	Formal verification meets robustness checking - Techniques and challenges. DDECS Rolf Drechsler, Görschwin Fey
2010	J	`jnl`	MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electron. Test. Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler
2010	A	`conf`	Polynomial datapath optimization using constraint solving and formal modelling. ICCAD Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler
2010	C	`conf`	RobuCheck: A Robustness Checker for Digital Circuits. DSD Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
2010	—	`conf`	RobuCheck: a robustness checker for digital circuits. DYADEM-FTS@EDCC Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
2010	—	`conf`	Towards Unifying Localization and Explanation for Automated Debugging. MTV Görschwin Fey, André Sülflow, Rolf Drechsler
2010	C	`conf`	Using QBF to increase accuracy of SAT-based debugging. ISCAS André Sülflow, Görschwin Fey, Rolf Drechsler
2009	J	`jnl`	Advanced verification by automatic property generation. IET Comput. Digit. Tech. Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
2009	A*	`conf`	Computing bounds for fault tolerance using formal techniques. DAC Görschwin Fey, André Sülflow, Rolf Drechsler
2009	—	`conf`	Deterministic Algorithms for ATPG under Leakage Constraints. Asian Test Symposium Görschwin Fey
2009	J	`jnl`	Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
2009	—	`conf`	Evaluation of Cardinality Constraints on SMT-Based Debugging. ISMVL André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
2009	—	`conf`	Increasing the Accuracy of SAT-based Debugging. MBMV André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
2009	A	`conf`	Increasing the accuracy of SAT-based debugging. DATE André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
2009	C	`conf`	Robustness Check for Multiple Faults Using Formal Techniques. DSD Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
2009	—	`conf`	SAT-based ATPG testing of inter- and intra-gate bridging faults. ECCTD Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada
2009	—	`book`	Test Pattern Generation using Boolean Proof Engines. Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
2009	C	`conf`	WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
2008	—	`conf`	A Basis for Formal Robustness Checking. ISQED Görschwin Fey, Rolf Drechsler
2008	J	`jnl`	Automatic Fault Localization for Property Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler
2008	A	`conf`	Automatic Generation of Complex Properties for Hardware Designs. DATE Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
2008	—	`conf`	Debugging Design Errors by Using Unsatisfiable Cores. MBMV André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
2008	C	`conf`	Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. DSD Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler
2008	J	`jnl`	On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille
2008	J	`jnl`	On the construction of small fully testable circuits with low depth. Microprocess. Microsystems Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
2008	—	`book`	Robustness and usability in modern design flows. Görschwin Fey, Rolf Drechsler
2008	—	`conf`	SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
2008	—	`conf`	Targeting Leakage Constraints during ATPG. ATS Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
2008	—	`conf`	Using unsatisfiable cores to debug multiple design errors. ACM Great Lakes Symposium on VLSI André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
2007	C	`conf`	Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
2007	—	`conf`	Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
2007	—	`conf`	Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
2007	C	`conf`	Instance Generation for SAT-based ATPG. DDECS Daniel Tille, Görschwin Fey, Rolf Drechsler
2007	C	`conf`	On the Construction of Small Fully Testable Circuits with Low Depth. DSD Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
2007	Misc	`conf`	Reusing Learned Information in SAT-based ATPG. VLSI Design Görschwin Fey, Tim Warode, Rolf Drechsler
2007	C	`conf`	SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
2007	—	`conf`	SWORD: A SAT like Prover Using Word Level Information. VLSI-SoC (Selected Papers) Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
2007	C	`conf`	SWORD: A SAT like prover using word level information. VLSI-SoC Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
2007	—	`conf`	Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse. MBMV André Sülflow, Görschwin Fey, Rolf Drechsler
2006	Misc	`conf`	An Integrated Approach for Combining BDD and SAT Provers. VLSI Design Rolf Drechsler, Görschwin Fey, Sebastian Kinder
2006	—	`conf`	Automatic Fault Localization for Property Checking. Haifa Verification Conference Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler
2006	—	`conf`	Automatic Test Pattern Generation. SFM Rolf Drechsler, Görschwin Fey
2006	A	`conf`	Avoiding false negatives in formal verification for protocol-driven blocks. DATE Görschwin Fey, Daniel Große, Rolf Drechsler
2006	—	`conf`	Efficiency of Multi-Valued Encoding in SAT-based ATPG. ISMVL Görschwin Fey, Junhao Shi, Rolf Drechsler
2006	—	`—`	Increasing robustness and usability of circuit design tools by using formal techniques. Görschwin Fey
2006	—	`ch.`	Increasing robustness and usability of circuit design tools by using formal techniques. Ausgezeichnete Informatikdissertationen Görschwin Fey
2006	J	`jnl`	Minimizing the number of paths in BDDs: Theory and algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Görschwin Fey, Rolf Drechsler
2006	A	`conf`	On the relation between simulation-based and SAT-based diagnosis. DATE Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
2006	—	`conf`	SAT-based Calculation of Source Code Coverage for BMC. MBMV Görschwin Fey, Rolf Drechsler
2005	—	`book`	Advanced BDD optimization. Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler
2005	—	`conf`	Bridging fault testability of BDD circuits. ASP-DAC Junhao Shi, Görschwin Fey, Rolf Drechsler
2005	—	`conf`	Controlling the Memory During Manipulation of Word-Level Decision Diagrams. ISMVL Sebastian Kinder, Görschwin Fey, Rolf Drechsler
2005	—	`conf`	PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
2005	C	`conf`	SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
2005	—	`conf`	Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler
2004	—	`conf`	Algorithms for Taylor Expansion Diagrams. ISMVL Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski
2004	C	`conf`	BDD Circuit Optimization for Path Delay Fault Testability. DSD Görschwin Fey, Junhao Shi, Rolf Drechsler
2004	A	`conf`	Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. DATE Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey
2004	—	`conf`	Disjoint Sum of Product Minimization by Evolutionary Algorithms. EvoWorkshops Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler
2004	—	`conf`	Improving simulation-based verification by means of formal methods. ASP-DAC Görschwin Fey, Rolf Drechsler
2004	J	`jnl`	Synthesis of fully testable circuits from BDDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rolf Drechsler, Junhao Shi, Görschwin Fey
2003	—	`conf`	BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. Asian Test Symposium Junhao Shi, Görschwin Fey, Rolf Drechsler
2003	—	`conf`	Cost-efficient Formal Block Verification for ASIC Design. MBMV Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey
2003	C	`conf`	Finding Good Counter-Examples to Aid Design Verification. MEMOCODE Görschwin Fey, Rolf Drechsler
2003	—	`conf`	Modeling Multi-Valued Circuits in SystemC. ISMVL Daniel Große, Görschwin Fey, Rolf Drechsler
2003	—	`conf`	MuTaTe: an efficient design for testability technique for multiplexor based circuits. ACM Great Lakes Symposium on VLSI Rolf Drechsler, Junhao Shi, Görschwin Fey
2003	—	`conf`	Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. ISMVL Görschwin Fey, Sebastian Kinder, Rolf Drechsler
2002	—	`conf`	Minimizing the Number of Paths in BDDs. SBCCI Görschwin Fey, Rolf Drechsler