Gyu-Seob Jeong

30 papers A 1C 4Journal 17Unranked 8
YearRankTypeTitle / Venue / Authors
2021 J jnl
A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS.
IEEE Access
Byungjun Kang, Gyu-Seob Jeong, Jeongho Hwang, Kwanseo Park, Hyungrok Do, Hyojun Kim, Han-Gon Ko, Moon-Chul Choi, Deog-Kyoon Jeong
2020 J jnl
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Jeongho Hwang, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
2019 — conf
56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits.
OFC
Jeongho Hwang, Hyungrok Do, Hong-Seok Choi, Gyu-Seob Jeong, Daehyun Koh, Sungwoo Kim, Deog-Kyoon Jeong
2019 — conf
A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS.
VLSI Circuits
Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog-Kyoon Jeong
2019 J jnl
A Modulo-FIR Equalizer for Wireline Communications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gyu-Seob Jeong, Byungjun Kang, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong
2019 J jnl
Reference Spur Reduction Techniques for a Phase-Locked Loop.
IEEE Access
Han-Gon Ko, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2018 J jnl
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs
Gyu-Seob Jeong, Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han-Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2018 A conf
4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS.
ISLPED
Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Seong Ho Park, Deog-Kyoon Jeong
2018 J jnl
A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Jeongho Hwang, Gyu-Seob Jeong, Woo-Rham Bae, Jun-Eun Park, Chang-Soo Yoon, Jungmin Yoon, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2018 J jnl
A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Hong-Seok Choi, Jeongho Hwang, Gyu-Seob Jeong, Gyungock Kim, Deog-Kyoon Jeong
2018 — conf
A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS.
VLSI Circuits
Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Deog-Kyoon Jeong
2018 — conf
A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS.
BCICTS
Jeongho Hwang, Gyu-Seob Jeong, Sang-Hyeok Chu, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
2017 J jnl
A 0.015-mm
IEEE Trans. Circuits Syst. II Express Briefs
Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong
2017 J jnl
A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G
IEEE Trans. Circuits Syst. II Express Briefs
Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong
2017 J jnl
Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.
Sensors
Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong
2016 J jnl
20-Gb/s 5-V
IEEE Trans. Circuits Syst. II Express Briefs
Yoonsoo Kim, Gyu-Seob Jeong, Jun-Eun Park, Joonbae Park, Gyungock Kim, Deog-Kyoon Jeong
2016 J jnl
A 0.36 pJ/bit, 0.025 mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong
2016 J jnl
A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2016 J jnl
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G
IEEE J. Solid State Circuits
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2016 C conf
A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme.
ISCAS
Haram Ju, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2016 C conf
A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS.
ISCAS
Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2016 J jnl
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Woo-Rham Bae, Gyu-Seob Jeong, Yoonsoo Kim, Hankyu Chi, Deog-Kyoon Jeong
2015 C conf
A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.
ISCAS
Kwanseo Park, Woo-Rham Bae, Haram Ju, Jinhyung Lee, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
2015 — conf
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.
A-SSCC
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2015 J jnl
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process.
IEEE J. Solid State Circuits
Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2015 J jnl
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection.
IEEE Trans. Circuits Syst. II Express Briefs
Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
2015 — conf
An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation.
VLSIC
Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
2014 — conf
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.
ESSCIRC
Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong
2014 C conf
A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS.
ISCAS
Gyu-Seob Jeong, Hankyu Chi, Kyungock Kim, Deog-Kyoon Jeong
2014 — conf
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process.
A-SSCC
Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong