Gwenolé Corre

19 papers C 1Misc 1Journal 7Unranked 10

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	FPGA Implementation of MLP, 1D-CNN and TTTratio algorithms for Neutron/Gamma-ray Discrimination using Plastic Scintillator. NorCAS Ali Hachem, Imane Belalchheb, Yoann Moline, Frédérick Carrel, Gwenolé Corre
2022	J	`jnl`	A Comprehensive Survey of Visual SLAM Algorithms. Robotics Andréa Macario Barros, Maugan Michel, Yoann Moline, Gwenolé Corre, Frédérick Carrel
2018	—	`conf`	High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques. IPDPS Workshops Tien Thanh Nguyen, Mathieu Thevenin, Anthony Mouraud, Gwenolé Corre, Olivier Pasquier, Sébastien Pillement
2017	—	`conf`	Model-driven reliability evaluation for MPSoC design. DASIP Tien Thanh Nguyen, Anthony Mouraud, Mathieu Thevenin, Gwenolé Corre, Olivier Pasquier, Sébastien Pillement
2016	—	`conf`	A Scalable Design Approach to Efficiently Map Applications on CGRAs. ISVLSI Satyajit Das, Thomas Peyret, Kevin J. M. Martin, Gwenolé Corre, Mathieu Thevenin, Philippe Coussy
2014	—	`conf`	An automated design approach to map applications on CGRAs. ACM Great Lakes Symposium on VLSI Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin J. M. Martin, Philippe Coussy
2014	—	`conf`	Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations. ASAP Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin J. M. Martin, Philippe Coussy
2008	J	`jnl`	Estimation et optimisation de la consommation des mémoires. Tech. Sci. Informatiques Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
2006	J	`jnl`	A Memory Aware High Level Synthesis Too CoRR Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
2006	J	`jnl`	High-level synthesis under I/O Timing and Memory constraints CoRR Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
2006	J	`jnl`	Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power CoRR Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
2006	J	`jnl`	Memory Aware High-Level Synthesis for Embedded Systems CoRR Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
2006	J	`jnl`	Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI CoRR Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin
2005	—	`conf`	A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. ICASSP (5) Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
2005	—	`conf`	High-level synthesis under I/O timing and memory constraints. ISCAS (1) Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin
2004	—	`conf`	A Memory Aware High Level Synthesis Tool . ISVLSI Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
2004	—	`conf`	A memory aware behavioral synthesis tool for real-time VLSI circuits. ACM Great Lakes Symposium on VLSI Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
2004	C	`conf`	Memory Aware HLS and the Implementation of Ageing Vectors. DSD Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
2004	Misc	`conf`	Memory accesses management during high level synthesis. CODES+ISSS Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin